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Description  |
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RELATED APPLICATION
This application claims priority from Korean Application No. 00-70489,
filed Nov. 24, 2000, the disclosure of which is hereby incorporated herein
by reference.
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices, and more
particularly to semiconductor memory devices containing delay locked loop
circuits and methods of operating same.
BACKGROUND OF THE INVENTION
Many integrated circuit devices (e.g., memory devices) operate in-sync with
externally supplied clock signals by generating one or more internal clock
signals that are preferably phase locked with the external clock signal
and with each other. As will be understood by those skilled in the art,
accurate phase locking of clock signals can be especially important for
integrated circuit devices, such as semiconductor memory devices, that
operate at high frequencies. Such integrated circuit devices may include
merged memory with logic (MML) devices, Rambus DRAM devices and double
data rate synchronous DRAM devices (DDR-SDRAM). Semiconductor memory
devices such as a selected circuit DRAM generally provide a power down
mode for deactivating selected circuit blocks inside the DRAM. In other
words, some, but not all, of the circuit blocks inside the DRAM may be
deactivated in order to reduce power consumption by the DRAM.
The power down modes of a DRAM may include an active power down mode, a
precharge power down mode, and a self-refresh mode. When the DRAM is in
the active power down mode or the precharge power down mode, all input
buffers excluding an input buffer connected to a system clock (CLK) pin
and an input buffer connected to a clock enable (CKE) pin are typically
deactivated. Therefore, power consumption may be reduced in the active
power down mode and the precharge power down mode. When the active power
down mode or the precharge power down mode proceed for more than a
predetermined time, all the data stored in the DRAM is generally lost.
In the self refresh mode, the data stored in the DRAM is refreshed and
maintained, typically by a signal automatically generated inside the DRAM.
This distinguishes the self refresh mode from the active power down mode
and the precharge power down mode. In the self refresh mode, a delay
locked loop circuit of the DRAM is also typically deactivated.
The DRAM generally also has a standby mode (or an idle mode), which is a
preparatory state, in which an active command or a mode register set (MRS)
command can typically be performed. When the mode of the DRAM transitions
from the self refresh mode to the standby mode, the DRAM generally
immediately starts operating the delay locked loop circuit and
synchronizing a system clock and an internal clock for several hundred
cycles. The delay locked loop continues to operate during the standby
mode.
Thus, in a conventional DRAM, because the delay locked loop circuit
generally continuously operates in the standby mode, power consumption by
the DRAM may be increased.
SUMMARY OF THE INVENTION
In accordance with various embodiments of the present invention, clock
generating circuits for a semiconductor memory device are provided. The
clock generating circuits include a delay locked loop (DLL) circuit that
generates an internal clock signal for the semiconductor memory device. A
control circuit activates the delay locked loop circuit for a
predetermined time when the semiconductor memory device transitions from a
self refresh mode, in which the DLL circuit is deactivated, to a standby
mode. The control circuit may also be configured to deactivate the DLL
circuit when the semiconductor memory device transitions from a power down
mode, in which the DLL circuit is activated, to the standby mode. The
semiconductor memory device may be a dynamic random access memory device
and the predetermined time may be a number of clock cycles of the internal
clock signal.
In further embodiments of the present invention, the control circuit
includes a first control circuit that generates a control signal that is
enabled for the predetermined time responsive to a first signal that
indicates the semiconductor memory device has transitioned from the self
refresh mode to the standby mode. A second control circuit activates the
DLL circuit responsive to the first signal and deactivates the DLL circuit
responsive to the control signal and responsive to a second signal that
indicates the semiconductor memory device has transitioned from the power
down mode to the standby mode.
In other embodiments of the present invention, the first control circuit
includes a control signal generating circuit that outputs the control
signal responsive to the first signal and a time out signal. The first
control circuit further includes a counter circuit that generates the time
out signal responsive to the control signal. The second control circuit
may include a set pulse generating circuit that generates a set pulse
signal responsive to the first signal and a reset pulse generating circuit
that generates a reset pulse signal responsive to the control signal. A
standby signal generating circuit activates the DLL circuit responsive to
the set pulse and deactivates the DLL circuit responsive to the reset
pulse signal and responsive to the second signal.
The set pulse generating circuit may include a delay circuit that
determines a pulse width of the set pulse signal. The reset pulse
generating circuit may include a delay circuit that determines a pulse
width of the reset pulse signal. The predetermined time during which the
DLL is activated after the standby mode is entered from the self refresh
mode may be no less than an expected lock time for the DLL circuit. The
predetermined time may be specified as a number of clock cycles of the
internal clock signal. The power down mode may be a precharge power down
mode.
In further aspects of the present invention, methods are provided for
controlling a clock generating circuit of a semiconductor memory device. A
delay locked loop (DLL) circuit of the clock generating circuit is
activated when the semiconductor memory device transitions to a standby
mode from a self refresh mode in which the DLL circuit is deactivated. The
DLL circuit is then deactivated a predetermined time after the
semiconductor memory device transitions to the standby mode from the self
refresh mode. In further embodiments, the DLL circuit is also deactivated
when the semiconductor memory device transitions to the standby mode from
a power down mode in which the DLL circuit is activated.
In yet other embodiments of the present invention, semiconductor memory
devices are provided which have a self refresh mode, a precharge power
down mode, and a standby mode and which operate in synchronization with a
system clock signal. The semiconductor memory device includes a delay
locked loop circuit for generating an internal clock signal in
synchronization with the system clock signal. The device further includes
a control circuit for activating the delay locked loop circuit during a
predetermined clock cycle of the internal clock signal when the mode of
the semiconductor memory device is converted from the self refresh mode
into the standby mode and then, deactivating the delay locked loop circuit
and deactivating the delay locked loop circuit when the mode of the
semiconductor memory device is converted from the precharge power down
mode into the standby mode.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram illustrating a clock generating circuit in a
dynamic random access memory (DRAM) according to embodiments of the
present invention;
FIG. 2 is a circuit diagram illustrating the control signal generating
circuit shown in FIG. 1 according to embodiments of the present invention;
FIG. 3 is a circuit diagram illustrating the counter circuit shown in FIG.
1 according to embodiments of the present invention;
FIG. 4 is a circuit diagram illustrating the one bit counters shown in FIG.
3 according to embodiments of the present invention;
FIG. 5 is a circuit diagram illustrating the first pulse signal generating
circuit shown in FIG. 1 according to embodiments of the present invention;
FIG. 6 is a circuit diagram illustrating the second pulse signal generating
circuit shown in FIG. 1 according to embodiments of the present invention;
FIG. 7 is a circuit diagram illustrating the standby signal generating
circuit shown in FIG. 1 according to embodiments of the present invention;
FIG. 8 is a timing diagram illustrating the operation of a clock generating
circuit in a DRAM according to embodiments of the present invention when
the mode of the DRAM transitions from a self refresh mode to a standby
mode; and
FIG. 9 is a timing diagram illustrating operation of a clock generating
circuit in a DRAM according to embodiments of the present invention when
the mode of the DRAM transitions from a precharge power down mode to the
standby mode.
DESCRIPTION OF PREFERRED EMBODIMENTS
The present invention will now be described more fully hereinafter with
reference to the accompanying drawings, in which preferred embodiments of
the invention are shown. This invention may, however, be embodied in
different forms and should not be construed as limited to the embodiments
set forth herein. Rather, these embodiments are provided so that this
disclosure will be thorough and complete, and will fully convey the scope
of the invention to those skilled in the art. Like numbers refer to like
elements throughout and signal lines and signals thereon may be referred
to by the same reference symbols. While the present invention is generally
described herein with reference to embodiments in which an active state
(set or "1") is a high voltage and an inactive (reset or "0") is a low
voltage, it is to be understood that the present invention may also be
implemented with a complementary logic in which the active state is a low
voltage and the inactive state is a high voltage. Similarly, for such
complementary logic embodiments reference to a rising edge herein is still
to be understood as referring to a transition from an inactive state to an
active state even though the associated voltage change is from a high to a
low voltage.
FIG. 1 is a block diagram showing a clock generating circuit in a dynamic
random access memory (DRAM) according to embodiments of the present
invention. Various components of the DRAM not related to the present
invention are not illustrated in FIG. 1 as they will be generally
understood by those of skill in the art without further description
herein.
Referring to FIG. 1, the DRAM includes a delay locked loop circuit 15 and
first and second control circuits 11 and 13 that may reduce power
consumption by the delay locked loop circuit 15 when the DRAM is in a
standby mode.
The delay locked loop circuit 15 illustrated in FIG. 1 is a circuit which
may be used in a synchronous DRAM to generate an internal clock signal
PCLK in synchronization with a system clock signal CLK. The DLL circuit 15
may consume significant amounts of power when it is activated (enabled).
The first control circuit 11 generates a control signal PDLLCNT, which is
enabled in response to a signal PSELF. The PSELF signal indicates whether
the DRAM is in self refresh mode and, thus, may be used to indicate when
the DRAM has transitioned from the self refresh mode into a standby mode.
The PDLLCNT signal is disabled (deactivated) a predetermined time, such as
a selected number of clock cycles, after the transition to standby mode.
The predetermined time may be of a duration no less than the expected
locking time of the delay locked loop circuit 15 after the mode of the
DRAM transitions from the self refresh mode to the standby mode.
Therefore, the predetermined time is preferably greater than the locking
time of the delay locked loop circuit 15. In various embodiments of the
present invention, a time of about 256 cycles is provided. The locking
time as used herein is the expected time needed for the delay locked loop
circuit 15 to be locked.
As shown in FIG. 1, the first control circuit 11 includes a control signal
generating circuit 11a and a counter circuit 11b. The control signal
generating circuit 11a generates the control signal PDLLCNT in response to
the signal PSELF indicating that the mode of the DRAM has transitioned
from the self-refresh mode to the standby mode and to a signal PCNT256
indicating when the predetermined number of clock cycles has passed. Thus,
the control signal PDLLCNT is enabled in response to the signal PSELF,
which indicates that the mode of the DRAM is converted into the standby
mode, and is disabled in response to the signal PCNT256, which indicates
that the predetermined number of clock cycles has passed. The counter
circuit 11b counts cycles of the internal clock signal PCLK in response to
the control signal PDLLCNT and generates the signal PCNT256, which
indicates that the predetermined clock cycle has passed.
The second control circuit 13 activates the delay locked loop circuit 15 in
response to the signal PSELF, indicating that the mode of the DRAM has
converted from the self refresh mode into the standby mode, and
deactivates the delay locked loop circuit 15 when the control signal
PDLLCNT is disabled. As shown in FIG. 1, the delay locked loop circuit 15
may also be disabled (deactivated) in response to a signal CKEBPU, which
indicates that the mode of the DRAM has transitioned from the precharge
power down mode into the standby mode.
More particularly, the second control circuit 13 includes a first pulse
signal generating circuit 13a, a second pulse signal generating circuit
13b, and a standby signal generating circuit 13c. The first pulse signal
generating circuit 13a generates a first pulse signal PDLLRESET in
response to the signal PSELF, indicating that the mode of the DRAM has
transitioned from the self refresh mode into the standby mode. The second
pulse signal generating circuit 13b generates a second pulse signal PICC
in response to the disablement of the control signal PDLLCNT. The standby
signal generating circuit 13c generates a standby signal STANDBY that
activates the delay locked loop circuit 15 in response to the first pulse
signal PDLLRESET and deactivates the delay locked loop circuit 15 in
response to the second pulse signal PICC or the signal CKEBPU.
As a result, the first and second control circuits 11 and 13 activate the
delay locked loop 15 for a specified time (or number of clock cycles) when
the mode of the DRAM is transitioned from the self refresh mode to the
standby mode, and deactivate the delay locked loop circuit 15. The
activated state may be more than the time needed or expected for the delay
locked loop circuit 15 to lock. Also, the first and second control
circuits 11 and 13 may immediately deactivate the delay locked loop
circuit 15 when the mode of the DRAM transitions from the power down mode
into the standby mode. This deactivation of the delay locked loop circuit
15 in the standby mode, may reduce power consumption by a semiconductor
memory device including the delay locked loop circuit 15.
In the DRAM, the self refresh mode, the precharge power down mode, and the
standby mode are generally set by controlling the logic states of a system
clock CLK pin, a row address strobe RASB pin, a column address strobe CASB
pin, a chip selection CSB pin, a write enable WEB pin, and a clock enable
CKE pin. As operation of these aspects of the DRAM will be understood by
those skilled in the art, detailed description thereof will not be
presented herein.
The signal PSELF, which indicates that the mode of the DRAM has
transitioned from the self refresh mode into the standby mode, and the
signal CKEBPU, which indicates that the mode of the DRAM has transitioned
from the precharge power down mode into the standby mode are generated by
other circuitry inside the DRAM. When the self refresh mode is set, the
signal PSELF transitions to a logic "high" level . When the mode of the
DRAM transitions from the self refresh mode to the standby mode, the
signal PSELF transitions to a logic "low" level. When the precharge power
down mode is set, the signal CKEBPU transitions to the logic "high" level.
When the mode of the DRAM changes from the precharge power down mode to
the standby mode, the signal CKEBPU transitions to the logic "low" level.
FIG. 2 is a circuit diagram illustrating embodiments of a control signal
generating circuit 11a as shown in FIG. 1. The control signal generating
circuit 11a shown in FIG. 2 includes an inverter 21, NAND gates 22, 23,
and 24, and a NOR gate 25. The NAND gates 23 and 24 define a latch.
The signal PSELFD, which is the output signal of the delay circuit 54 shown
in FIG. 5, is obtained by delaying the signal PSELF for a predetermined
time. The signal PCNT256, which is the output signal of the counter
circuit 11b shown in FIG. 3, indicates when a predetermined clock cycle
has passed. As described by way of example herein for purposes of
explanation, the predetermined clock cycle is set to be 256 cycles. When
the 256 cycles have passed after the control signal PDLLCNT is enabled to
the logic "high" level, the signal PCNT256 is switched to the logic "high"
level. The signals PRA and PVCCH are not directly pertinent to the present
invention. The signal PRA switches to the logic "low" level when the DRAM
is in a precharge state. The signal PVCCH switches from the logic "low"
level, which is an initial state, to the logic "high" level.
To be more specific, the signal PSELF is at the logic "high" level in the
self refresh mode. Accordingly, the control signal PDLLCNT is placed in
the logic "low" level. When the mode of the DRAM is switched from the self
refresh mode into the standby mode, the signal PSELF is switched to the
logic "low" level. As the signal PSELFD is at the logic "high" level, the
control signal PDLLCNT is switched to the logic "high" state. Also, the
control signal PDLLCNT is held at the logic "high" level by a latch
structure. When the 256 cycles have passed after the control signal
PDLLCNT is enabled to the logic "high" level, the signal PCNT256 is
switched to the logic "high" level and the control signal PDLLCNT switches
to the logic "low" level.
FIG. 3 is a circuit diagram illustrating embodiments of the counter circuit
11b shown in FIG. 1. The counter circuit 11b, which is an eight bit
counter circuit in FIG. 3, counts the 256 cycles. The counter circuit 11b
includes eight one bit counters 300 through 307, NAND gates 308 through
314, NOR gates 315 through 318, and inverters 319 through 427.
When the signal PDLLCNT is at the logic "low" level, the one bit counters
300 through 307 are all reset. Accordingly, the output signals DLLCNT0
through DLLCNT7 are switched to the logic "low" level. The signal PCNT256,
therefore, is switched to the logic "low" level. When the signal PDLLCNT
is at the logic "high" level, the outputs of the counter, which are
constituted of DLLCNTO through DLLCNT7, sequentially increase. When the
256 cycles have passed after the signal PDLLCNT transitions to the logic
"high" level, the outputs DLLCNTO through DLLCNT7 are all switched to the
logic "high" level. Accordingly, the signal PCNT256 is switched to the
logic "high" level.
FIG. 4 is a circuit diagram illustrating embodiments of the one bit
counters 300 through 307 shown in FIG. 3. Each of the one bit counters 300
through 307 include a NOR gate 40, inverters 41 through 46, transmission
gates 47 and 48, and a pull down NMOS transistor 49.
The output signal of the inverter 319 shown in FIG. 3 is input to an input
stage 11 and the output signal of the inverter 320 is input to an input
stage 12. The carry of the previous one bit counter is input to an input
stage 13. As the operations of the one bit counters are generally
understood by those of skill in the art, further detailed description
thereof will not be provided herein.
FIG. 5 is a circuit diagram illustrating embodiments of the first pulse
signal generating circuit 13a shown in FIG. 1. The first pulse signal
generating circuit 13a includes inverters 51 and 53, a NAND gate 52, and a
delay circuit 54.
The first pulse signal generating circuit 13a, as shown in FIG. 5 is a
positive pulse signal generating circuit which generates a first pulse
signal PDLLRESET having a positive pulse corresponding to the delay time
of the delay circuit 54 when the signal PSELF transitions from the logic
"high" level to the logic "low" level.
FIG. 6 is a circuit diagram illustrating embodiments of the second pulse
signal generating circuit 13b shown in FIG. 1. The second pulse signal
generating circuit 13b as shown in FIG. 6 includes a NOR gate 61 and an
inversion delay circuit 63. The second pulse signal generating circuit
13b, is shown as a positive pulse signal generating circuit that generates
a second pulse signal PICC having a positive pulse corresponding to the
delay time of the inverting delay circuit 63 when the signal PDLLCNT
transitions from the logic "high" level to the logic "low" level.
FIG. 7 is a circuit diagram illustrating embodiments of the standby signal
generating circuit 13c shown in FIG. 1. The standby signal generating
circuit 13c includes inverters 701 through 710, NAND gates 711 through
714, a NOR gate 715, pull up PMOS transistors 716 through 719, pull down
NMOS transistors 720 through 722, a transmission gate 723, and fuses F1
and F2.
A signal PDLLOFF, which is established in a mode register set (MRS) mode
after the power up of the DRAM, determines whether the delay locked loop
circuit 15 shown in FIG. 1 is used or not. When the signal PDLLOFF is at
the logic "high" level, the standby signal STANDBY is placed at the logic
"high" level. Accordingly, the delay locked loop circuit 15 shown in FIG.
1 is deactivated. In other words, the delay locked loop circuit 15 does
not operate and need not consume power.
A signal MRSET corresponds to MRS. When the signal MRSET is switched to the
logic "high" level, the standby signal STANDBY is switched to the logic
"high" level. Accordingly, the delay locked loop circuit 15 is
deactivated. A signal FSEBRD indicates whether the DRAM is performing a
read operation. When the signal FSEBRD is at the logic "low", it means
that the DRAM is performing the read operation. A signal FSEBWR indicates
whether the DRAM is performing a write operation. When the signal FSEBWR
is at the logic "low" level, it means that the DRAM performs a write
operation. When the signal FSEBRD is at the logic "low" level or when the
signal FSEBWR is at the logic "low" level, the standby signal STANDBY is
switched to the logic "low" level. Accordingly, the delay locked loop
circuit 15 operates normally.
A signal PAIVCEB indicates that a memory cell array voltage generation
circuit used inside the DRAM is operating. A signal PRDQ indicates that
the row address of the DRAM is activated. The signals MRSET, FSEBRD,
FSEBWR, PAIVCEB, PRDQ, and PDLLOFF do not impact on the description of the
present invention. When the DRAM for the illustrated examples is in the
precharge power down mode or the self refresh mode, the signals MRSET,
PRDQ, and PDLLOFF are all at the logic "low" level and the signals FSEBRD,
FSEBWR, and PAIVCEB are all at the logic "high" level.
A signal PDLLRESET, which is a pulse signal generated by the first pulse
signal generating circuit 13a shown in FIG. 5, resets the delay locked
loop circuit 15 shown in FIG. 1 and makes the delay locked loop circuit 15
start locking operations. When the signal PDLLRESET is at the logic "high"
level, namely, when the mode of the DRAM is converted from the self
refresh mode into the standby mode, the pull up PMOS transistor 717 is
turned on. Accordingly, the output of the latch defined by the inverters
705 and 706 is switched to the logic "low" level. Therefore, the output of
the NAND gate 713 is switched to the logic "high" level. At this time,
since the signal PVCCH is at the logic "high" level and the fuse F1 is not
cut off, the transmission gate 723 is already turned on. Therefore, the
standby signal STANDBY is switched to the logic "low" level. Accordingly,
the delay locked loop circuit 15 shown in FIG. 1 is activated and begins
to operate.
When the signal PICC is switched to the logic "high" level, namely, when
the mode of the DRAM changes from the self refresh mode into the standby
mode and then the 256 cycles have passed, the pull down NMOS transistor
722 is turned on. Accordingly, the output of the latch defined by of the
inverters 705 and 706 is switched to the logic "high | | |
