Dual-port DRAM architecture system - Patent Review 6545935

Claims

We claim:

1. A memory system comprising a plurality of dynamic random access memory (DRAM) cells arranged in an array, each of the DRAM cells having a corresponding first port and a corresponding second port, each first and second port coupled to a sense amplifier and enabling access to the corresponding DRAM cell, wherein said memory system prioritizes simultaneous access requests slated through said first and second ports of each DRAM cell.

2. The memory system according to claim 1, wherein said memory system prioritizes a write or read access request slated through said first port at a higher priority than a simultaneous read or refresh access request slated through said second port.

3. The memory system according to claim 1, wherein said memory system prioritizes a write access request slated through said second port at a higher priority than a simultaneous write or read access request slated through said first port.

4. The memory system according to claim 1, wherein said first port enables accesses to the corresponding DRAM cell selected from the group consisting of read and write accesses, and said second port enables accesses to the corresponding DRAM cell selected from the group consisting of read, write and refresh accesses.

5. The memory system according to claim 1, wherein said prioritized simultaneous access requests include a write access request slated through said first port and a read access request slated through said second port for writing and reading data simultaneously.

6. The memory system according to claim 5, wherein said write and read access requests are performed by said memory system by writing the data to the corresponding DRAM cell through said first port and by simultaneously writing the data through to an output bus.

7. The memory system according to claim 1, wherein said prioritized simultaneous access requests include a read access request slated through said first port and a write access request slated through said second port for reading and writing data simultaneously.

8. The memory system according to claim 7, wherein said read and write access requests are performed by said memory system by writing the data to the corresponding DRAM cell through said second port and by simultaneously writing the data through to an output bus.

9. The memory system according to claim 1, wherein said first port enables access to the corresponding DRAM cell during a first half of a clock cycle and said second port enables access to the corresponding DRAM cell during a second half of said clock cycle.

10. The memory system according to claim 1, further comprising a refresh address generator for generating an address corresponding to a DRAM cell requiring a refresh access through said second port.

11. The memory system according to claim 10, wherein said address is stored within an address buffer if said second port is accessed for a read or write operation.

12. The memory system according to claim 1, further comprising:

a first wordline driver circuit coupled to said first port of each of the DRAM cells; and

a second wordline driver circuit coupled to said second port of each of the DRAM cells.

13. The memory system according to claim 12, wherein said first wordline driver circuit and said second wordline driver circuit are located on opposite sides of the array.

14. The memory system according to claim 12, wherein said first wordline driver circuit and said second wordline driver circuit are located on the same side of the array.

15. The memory system according to claim 1, further comprising:

a first sense amplifier circuit coupled to said first port of each of the DRAM cells; and

a second sense amplifier circuit coupled to said second port of each of the DRAM cells.

16. The memory system according to claim 15, wherein said first sense amplifier circuit and said second sense amplifier circuit are located at opposite sides of the array.

17. The memory system according to claim 1, further comprising a first and a second pair of bitlines for each of the DRAM cells, where the first pair connects said first port of each of the DRAM cells to a first sense amplifier circuit and the second pair connects said second port of each of the DRAM cells to a second sense amplifier circuit, where the pairing of bitlines suppresses noise due to coupling during operation of the memory system.

18. The memory system according to claim 17, wherein the first and second pair of bitlines are arranged in a twisted configuration.

19. The memory system according to claim 17, wherein the first pair of bitlines are coupled to a slave sense amplifier and the second pair of bitlines are coupled to a master sense amplifier.

20. The memory system according to claim 1, further comprising a pair of wordlines for each of the DRAM cells, where a first wordline of the pair of wordlines connects said first port to a first wordline driver circuit and a second wordline of the pair of wordlines connects said second port to a second wordline driver circuit.

21. The memory system according to claim 20, wherein said first and second wordline driver circuits are located on opposite sides of the array.

22. The memory system according to claim 20, wherein said first and second wordline driver circuits are located on the same side of the array.

23. The memory system according to claim 1, further comprising a first port control circuit and a second port control circuit for controlling access to said first and second ports, respectively.

24. The memory system according to claim 23, further comprising a comparator for receiving a first port row address and a second port row address and determining if said first port row address and said second port row address correspond to the corresponding DRAM cell.

25. The memory system according to claim 24, wherein said comparator includes an output node for transmitting a signal to said first port control circuit and said second port control circuit, said signal indicating if said first port row address and said second port row address correspond to the corresponding DRAM cell.

26. The memory system according to claim 25, wherein if said signal indicates that said first port row address and said second port row address correspond to the same row of DRAM cells as the corresponding DRAM cell in the array, a logic low second port control signal is transmitted to said second port control circuit to cause said second port control circuit to transmit a logic low signal to second port control circuitry to prevent access through said second port to the corresponding DRAM cell, otherwise a logic high second port control signal is transmitted to said second port control circuit to cause said second port control circuit to transmit a logic high signal to said second port control circuitry to allow access through said second port to the corresponding DRAM cell.

27. The memory system according to claim 25, wherein said signal is received by at least one multiplexer of said first port control circuit and at least one multiplexer of said second port control circuit, said signal being a control signal for each multiplexer.

28. The memory system according to claim 1, wherein a refresh access and a read access through said second port of the corresponding DRAM cell are performed non-simultaneously.

29. The memory system according to claim 1, further comprising:

a first decoder circuit coupled to said first port of each of the DRAM cells; and

a second decoder circuit coupled to said second port of each of the DRAM cells.

30. The memory system according to claim 29, wherein said first decoder circuit and said second decoder circuit are located on opposite sides of the array.

31. The memory system according to claim 29, wherein said first decoder circuit and said decoder driver circuit are located on the same side of the array.

32. A memory system comprising:

a plurality of dynamic random access memory (DRAM) cells arranged in an array, each of the DRAM cells having a corresponding first port and a corresponding second port, each first and second port coupled to a sense amplifier and enabling access to the corresponding DRAM cell; and

a traffic control system for prioritizing first and second simultaneous access requests for accessing the corresponding DRAM cell, where the first access request requests access to the corresponding DRAM cell through said first port and the second access request requests simultaneous access to the corresponding DRAM cell through said second port.

33. The memory system according to claim 32, wherein the first access request is a write access request slated through said first port and the second access request is a read access request slated through said second port for writing and reading data to the corresponding DRAM cell simultaneously.

34. The memory system according to claim 33, wherein said traffic control system enables said write access request and said read access request to be performed simultaneously by enabling the data to be written to the corresponding DRAM cell through said first port and to an output bus.

35. The memory system according to claim 32, wherein the first access request is a read access request slated through said first port and the second access request is a write access request slated through said second port for reading and writing data to the corresponding DRAM cell simultaneously.

36. The memory system according to claim 35, wherein said traffic control system enables said read access request and said write access request to be performed simultaneously by enabling the data to be written to the corresponding DRAM cell through said second port and to an output bus.

37. The memory system according to claim 32, wherein the first access request is a write access request slated through said first port and the second access request is a write access request slated through said second port for writing data to the corresponding DRAM cell simultaneously.

38. The memory system according to claim 37, wherein said traffic control system enables said write access request slated through said first port to be canceled and said write access request slated through said second port to be performed.

39. The memory system according to claim 32, wherein the first access request is a read access request slated through said first port and the second access request is a read access request slated through said second port for reading data from the corresponding DRAM cell simultaneously.

40. The memory system according to claim 39, wherein said traffic control system enables said read access request slated through said second port to be canceled and said read access request slated through said first port to be performed.

41. The memory system according to claim 32, wherein the first access request is performed during a first half of a clock cycle and the second access request is performed during a second half of said clock cycle.

42. The memory system according to claim 32, further comprising a refresh address generator for generating an address corresponding to a DRAM cell requiring a refresh access through said second port.

43. The memory system according to claim 42, wherein said address is stored within an address buffer if said second port is being accessed for a read or write operation.

44. The memory system according to claim 32, further comprising:

a first wordline driver circuit coupled to said first port of each of the DRAM cells; and

a second wordline driver circuit coupled to said second port of each of the DRAM cells.

45. The memory system according to claim 44, wherein said first wordline driver circuit and said second wordline driver circuit are located on opposite sides of the array.

46. The memory system according to claim 44, wherein said first wordline driver circuit and said second wordline driver circuit are located on the same side of the array.

47. The memory system according to claim 32, further comprising:

a first sense amplifier circuit coupled to said first port of each of the DRAM cells; and

a second sense amplifier circuit coupled to said second port of each of the DRAM cells.

48. The memory system according to claim 47, wherein said first sense amplifier circuit and said second sense amplifier circuit are located at opposite sides of the array.

49. The memory system according to claim 32, further comprising a first and a second pair of bitlines for each of the DRAM cells, where the first pair connects said first port of each of the DRAM cells to a first sense amplifier circuit and the second pair connects said second port of each of the DRAM cells to a second sense amplifier circuit.

50. The memory system according to claim 49, further comprising at least one pair of complementary bitlines and at least one wordline coupled to each of the at least one pair of complementary bitlines, where the at least one pair of complementary bitlines suppresses coupling noise due to coupling by the at least one wordline during operation of the memory system.

51. The memory system according to claim 50, wherein the at least one pair of complementary bitlines are arranged in a twisted configuration.

52. The memory system according to claim 32, further comprising a pair of wordlines for each of the DRAM cells, where a first wordline of the pair of wordlines connects said first port to a first wordline driver circuit and a second wordline of the pair of wordlines connects said second port to a second wordline driver circuit.

53. The memory system according to claim 52, wherein said first and second wordline driver circuits are located on opposite sides of the array.

54. The memory system according to claim 52, wherein said first and second wordline driver circuits are located on the same side of the array.

55. The memory system according to claim 32, wherein said traffic control system includes a first port control circuit and a second port control circuit for controlling access to the corresponding DRAM cell through said first and second ports, respectively.

56. The memory system according to claim 55, wherein said traffic control system includes a comparator for receiving a first port row address and a second port row address and determining if said first port row address and said second port row address correspond to the corresponding DRAM cell.

57. The memory system according to claim 56, wherein said comparator includes an output node for transmitting a signal to said first port control circuit and said second port control circuit indicating if said first port row address and said second port row address correspond to the corresponding DRAM cell.

58. The memory system according to claim 57, wherein if said signal indicates that said first port row address and said second port row address correspond to the same row of DRAM cells as the corresponding DRAM cell in the array, a logic low second port control signal is transmitted to said second port control circuit to cause said second port control circuit to transmit a logic low signal to second port control circuitry to prevent access through said second port to the corresponding DRAM cell, otherwise a logic high second port control signal is transmitted to said second port control circuit to cause said second port control circuit to transmit a logic high signal to said second port control circuitry to allow access through said second port to the corresponding DRAM cell.

59. The memory system according to claim 57, wherein said signal has a logic high level if said first port row address and said second port row address correspond to the corresponding DRAM cell, otherwise said signal has a logic low level.

60. The memory system according to claim 57, wherein said signal is received by at least one multiplexer of said first port control circuit and at least one multiplexer of said second port control circuit, said signal being a control signal for each multiplexer.

61. The memory system according to claim 32, further comprising:

a firs t decoder circuit coupled to said first port of each of the DRAM cells; and

a second decoder circuit coupled to said second port of each of the DRAM cells.

62. The memory system according to claim 61, wherein said first decoder circuit and said second decoder circuit are located on opposite sides of the array.

63. The memory system according to claim 61, wherein said first decoder circuit and said decoder driver circuit are located on the same side of the array.

64. A memory system comprising a plurality of dynamic random access memory (DRAM) cells arranged in an array, wherein:

each of the DRAM cells has a corresponding first port coupled to a sense amplifier and a corresponding second port coupled to a sense amplifier;

each first port enables both a read access and write access to the corresponding DRAM cell;

each second port enables both a read access and write access to the corresponding DRAM cell; and

the memory system enables one write access to the corresponding DRAM cell to be performed simultaneously with one read access to the corresponding DRAM cell.

65. The memory system according to claim 64, wherein the memory system enables one write access to be prioritized at a higher priority than a simultaneous write access to the corresponding DRAM cell.

66. The memory system according to claim 64, wherein the memory system enables one read access to be prioritized at a higher priority than a simultaneous read access to the corresponding DRAM cell.

67. A method of accessing a multi-port dynamic random access memory (DRAM) cell having a storage capacitor, a first port and a second port, the method comprising the steps of:

receiving a first access request for accessing the storage capacitor via the first port;

receiving a second access request for accessing the storage capacitor via the second port; and

prioritizing the first and second access requests prior to accessing the storage capacitor via the first port or second port.

68. The method according to claim 67, further comprising the step of simultaneously performing the first and second access requests, wherein one access request is performed without accessing the storage capacitor.

69. The method according to claim 67, wherein each of the DRAM cells in the same row is connected to a respective pair of wordlines and each of the DRAM cells in the same column is connected to two respective pairs of bitlines.

70. A memory system comprising:

a plurality of dynamic random access memory (DRAM) cells arranged in an array, each of the DRAM cells having a corresponding first port and a corresponding second port, each first and second port enabling access to the corresponding DRAM cell;

a traffic control system for prioritizing first and second simultaneous access requests for accessing the corresponding DRAM cell, where the first access request requests access to the corresponding DRAM cell through said first port and the second access request requests simultaneous access to the corresponding DRAM cell through said second port; and

a first and a second pair of bitlines for each of the DRAM cells, where the first pair connects said first port of each of the DRAM cells to a first sense amplifier circuit and the second pair connects said second port of each of the DRAM cells to a second sense amplifier circuit.

71. The memory system according to claim 70, further comprising:

a first wordline driver circuit coupled to said first port of each of the DRAM cells; and

a second wordline driver circuit coupled to said second port of each of the DRAM cells.

72. The memory system according to claim 71, wherein said first wordline driver circuit and said second wordline driver circuit are located on opposite sides of the array.

73. The memory system according to claim 71, wherein said first wordline driver circuit and said second wordline driver circuit are located on the same side of the array.

74. The memory system according to claim 70, further comprising at least one pair of complementary bitlines and at least one wordline coupled to each of the at least one pair of complementary bitlines, where the at least one pair of complementary bitlines suppresses coupling noise due to coupling by the at least one wordline during operation of the memory system.

75. The memory system according to claim 74, wherein the at least one pair of complementary bitlines are arranged in a twisted configuration.

76. The memory system according to claim 70, further comprising a pair of wordlines for each of the DRAM cells, where a first wordline of the pair of wordlines connects said first port to a first wordline driver circuit and a second wordline of the pair of wordlines connects said second port to a second wordline driver circuit.

77. The memory system according to claim 76, wherein said first and second wordline driver circuits are located on opposite sides of the array.

78. The memory system according to claim 76, wherein said first and second wordline driver circuits are located on the same side of the array.

79. The memory system according to claim 70, wherein said traffic control system includes a first port control circuit and a second port control circuit for controlling access to the corresponding DRAM cell through said first and second ports, respectively.

80. The memory system according to claim 70, wherein said traffic control system includes a comparator for receiving a first port row address and a second port row address and determining if said first port row address and said second port row address correspond to the corresponding DRAM cell.

81. The memory system according to claim 80, wherein said comparator includes an output node for transmitting a signal to said first port control circuit and said second port control circuit indicating if said first port row address and said second port row address correspond to the corresponding DRAM cell.

82. The memory system according to claim 81, wherein if said signal indicates that said first port row address and said second port row address correspond to the same row of DRAM cells as the corresponding DRAM cell in the array, a logic low second port control signal is transmitted to said second port control circuit to cause said second port control circuit to transmit a logic low signal to second port control circuitry to prevent access through said second port to the corresponding DRAM cell, otherwise a logic high second port control signal is transmitted to said second port control circuit to cause said second port control circuit to transmit a logic high signal to said second port control circuitry to allow access through said second port to the corresponding DRAM cell.

83. The memory system according to claim 81, wherein said signal has a logic high level if said first port row address and said second port row address correspond to the corresponding DRAM cell, otherwise said signal has a logic low level.

84. The memory system according to claim 81, wherein said signal is received by at least one multiplexer of said first port control circuit and at least one multiplexer of said second port control circuit, said signal being a control signal for each multiplexer.

85. The memory system according to claim 70, further comprising:

a first decoder circuit coupled to said first port of each of the DRAM cells; and

a second decoder circuit coupled to said second port of each of the DRAM cells.

86. The memory system according to claim 85, wherein said first decoder circuit and said second decoder circuit are located on opposite sides of the array.

87. The memory system according to claim 85, wherein said first decoder circuit and said decoder driver circuit are located on the same side of the array.

FIELD OF THE INVENTION

This invention relates to the field of integrated circuit (IC) design. Specifically, it relates to a dual-port dynamic random access memory (DRAM) architecture system.

BACKGROUND OF THE INVENTION

Each memory cell in a dual-port static random access memory (SRAM) chip is a buffer or flip-flop, and data is retained as long as power is maintained to the chip. SRAMs are realized with a bipolar technology, such as TTL, ECL, or I.sup.2 L or with MOS technology, such as NMOS or CMOS. Bipolar SRAMs are relatively fast, having access times of 10 to 100 nsec. Power dissipation is also high, typically, 0.1 to 1.0 mW/bit. By contrast, MOS RAM access time is typically 100 nsec and power dissipation is 25 .mu.W/bit. The combination of high circuit density, low power dissipation, and reasonable access time has led to the dominance of MOS technology in the manufacture of RAM. Hence, dual-port SRAMs having high-speed buffers are widely used in devices and equipment necessitating high-speed and high performance, such as microprocessors, communication networks, facsimile machines, modems, etc.

Since the memory cells of SRAMs take up a relatively large surface area on a single integrated (IC) chip, IC design engineers, in an effort to increase the number of memory cells on the IC chip and make the chip smaller, have focused on improving dynamic RAM (DRAM) chips to make them suitable for high-speed, high performance devices and equipment. Currently, the ultimate in compactness, is a single-port DRAM chip where each memory cell uses a capacitor to store a charge and one transistor to gate it to sense amplifier circuits as shown by the prior art DRAM cell 10 of FIG. 1.

The DRAM cell 10 includes an access transistor 12, a storage capacitor 14, a bitline 16 and a wordline 18. During a write access, a wordline enable signal is asserted on wordline 18 thereby turning on transistor 12. A data signal is provided on bitline 16. This signal is routed through transistor 12 and stored in capacitor 14. During a read access, a wordline enable signal is asserted on wordline 18 to turn on transistor 12. The data signal stored in capacitor 14 is routed to bitline 16 through transistor 12. This data signal is amplified by a sense amplifier circuit (not shown) and then provided to the device initiating the read access.

A disadvantage of the single-port DRAM cell 10 is that it does not enable multi-port access, where more than one port can be accessed for simultaneously enabling reading, writing and/or refreshing of the memory cell. Multi-port access is required if the DRAM chip is to compete with or surpass the SRAM chip in terms of high-speed and high performance, while being simple and compact. Further, the single-port DRAM cell 10 has two additional disadvantage common to all types of DRAM cells. That is, the charge of each DRAM cell must be restored after the cell is read, and the charge in every cell must be refreshed periodically by periphery refresh circuitry.

Hence, the data rate, in terms of data access time and refresh cycle time, is low for a DRAM chip which prevents IC design engineers from implementing DRAM chips in devices and equipment requiring high-speed and high performance, such as microprocessors and communication networks. It is therefore a goal of IC design engineers to design a dual-port DRAM architecture system which can simultaneously perform two data access requests slated for a DRAM cell for increasing the data array's data rate while maintaining its compactness. Such a DRAM architecture system would be a better design choice over an SRAM architecture system for devices and equipment necessitating high-speed and high performance.

A dual-port DRAM cell is described in U.S. Pat. No. 5,923,593. The dual-port DRAM cell as shown by FIG. 4 in the patent is designed for staggering the read accesses. That is, during the first half of a clock cycle the first port is accessed and during the second half of the clock cycle the second port is accessed. In a similar manner, write accesses can be staggered. That is, during the first half of the clock cycle, the first port is accessed for writing to a cell and during the second half of the clock cycle, the second port is accessed for writing to the same or a different cell. However, as noted in the patent, such a "simultaneous" write access results in an indeterminate data value being written to the DRAM cells which affects the integrity of the data.

For example, if in the first half of the clock cycle, a logic "one" is written into a cell while a logic "one" is latched into the sense amplifier circuit, the same row can be accessed through the second port during the second half of the clock cycle for writing a logic "zero". At this moment, due to charge sharing between the first sense amplifier circuit and the second sense amplifier circuit, the resulting charge stored in that cell will be in between "one" and "zero" and the data in the cell has an indeterminate data value. Similarly, a read-write access could also result in the same situation. For example, if a DRAM cell is originally stored with a logic "zero", after a read out operation through the first port during the first half of the clock cycle, a logic "zero" is latched in the first sense amplifier circuit. If the same row is accessed through the second port during the second half of the clock cycle, and is written with a logic "one", the data in the cell will again have an indeterminate data value due to charge sharing between the first sense amplifier circuit and the second sense amplifier circuit.

Additionally, the dual-port DRAM architecture system described in U.S. Pat. No. 5,923,593 is the classical open-bitline architecture system which is known to be susceptible to noise problems due to wordline-to-bitline coupling, bitline-to-bitline coupling, and bitline-to-substrate (or well) coupling which are well known in the DRAM industry. In an effort to mitigate the noise problems, the patent discloses the use of a dummy wordline swing in the adjacent array, as well as placing a dummy load in the edge array. However, with such a design configuration, the array size is significantly increased and operation of the dual-port DRAM becomes more complex.

SUMMARY

An objective of the present invention is to provide a dual-port DRAM architecture system for overcoming the disadvantages of the prior art.

Another objective of the present invention is to provide a dual-port DRAM architecture system for simultaneously performing two access requests slated for a DRAM cell without affecting the integrity of the data.

Further, another objective of the present invention is to provide a dual-port DRAM architecture system for prioritizing two simultaneous access requests slated for a DRAM cell.

Further still, another objective of the present invention is to provide a dual-port DRAM architecture system for suppressing noise due to wordline-to-bitline coupling, bitline-to-bitline coupling, and bitline-to-substrate coupling.

Accordingly, in an embodiment of the present invention, a dual-port, folded-bitline DRAM architecture system is presented which prioritizes two simultaneous access requests slated for a DRAM cell of a data array prior to performing at least one of the access requests to prevent affecting the integrity of the data while suppressing noise due to wordline-to-bitline coupling, bitline-to-bitline coupling, and bitline-to-substrate coupling. If the two access requests are read-refresh, read-read or write-refresh, where the first access request is slated through a first port and the second access request is slated through a second port of a corresponding DRAM cell of the data array, the system prioritizes the access request slated through the first port at a higher priority than the access request slated through the second port. The system thus cancels the access request slated through the second port. If the two access requests are write-read, the system prioritizes the two access requests as being equal to each other. The system then simultaneously performs the write and read access by accessing the corresponding DRAM cell through the first port to write the data while simultaneously writing the data through to an output bus, which is equivalent to a read access.

In another embodiment of the present invention, a dual-port, shared-address bus DRAM architecture system is presented which can perform two access requests in a staggered manner. That is, in a first half of a clock cycle, a DRAM cell is accessed through a first port to perform a first access request and in a second half of the clock cycle, the DRAM cell is accessed through a second port to perform a second access request.

Similarly to the folded-bitline DRAM architecture system, this system also prioritizes two simultaneous access requests slated for the DRAM cell of a data array. If the two access requests are read-refresh, read-read or write-refresh, where the first access request is slated through the first port and the second access request is slated through the second port of a corresponding DRAM cell of the data array, the system prioritizes the access request slated through the first port at a higher priority than the access request slated through the second port. The system thus cancels the access request slated through the second port.

If the two access requests are write-read or read-write, the system prioritizes the two access requests as being equal to each other. The system then simultaneously performs the write and read access or the read and write access requests by accessing the corresponding DRAM cell through the first port or second port, respectively, to write the data while simultaneously writing the data through to an output bus, which is equivalent to a read access. If the two access requests are write-write, the system prioritizes the write access request slated through the second port at a higher priority than the write access request slated through the first port. The system thus cancels the write access request slated through the first port.

This system further includes shared-address buses, thereby enabling control circuitry to be shared by both ports, since only one port of the corresponding DRAM cell can be used at a time due to staggering access requests. Hence, less control circuitry is required and all of the control circuitry can be provided at one side of the data array. Accordingly, the fabrication cost and the amount of surface area used in implementing the system are decreased.

Prioritization is realized, in order to maintain data integrity in both DRAM architecture systems, by designating one port of each DRAM cell a master port and the other port a slave port, where the access request slated through the master port has typically a higher priority than the access request slated through the slave port. Accordingly, accesses to the DRAM cell through the master port, with some exceptions, take precedence over accesses through the slave port.

Each DRAM architecture system suppresses noise due to wordline-to-bitline coupling, bitline-to-bitline coupling, and bitline-to-substrate coupling by providing at least a complementary bitline on the data array for each true bitline to form bitline pairs.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a schematic diagram of a prior art single-port DRAM cell;

FIG. 2 is a diagram of a dual-port, folded-bitline DRAM architecture system according to the present invention;

FIG. 3A is a diagram of a first dual-port DRAM data array arrangement for the dual-port, folded-bitline DRAM architecture system of FIG. 2;

FIG. 3B is a diagram of a second dual-port DRAM data array arrangement for the dual-port, folded-bitline DRAM architecture system of FIG. 2;

FIG. 3C is an enlarged view of a portion of FIG. 3B;

FIG. 4 is a waveform diagram of the operation of a master and a slave port of the dual-port, folded-bitline DRAM architecture system of FIG. 2;

FIG. 5 is a schematic diagram of a slave port control circuit of the dual-port, folded-bitline DRAM architecture system of FIG. 2;

FIG. 6 is a schematic diagram of a master port control circuit of the dual-port, folded-bitline DRAM architecture system of FIG. 2;

FIG. 7 is a schematic diagram of a priority circuit of the dual-port, folded-bitline DRAM architecture system of FIG. 2;

FIG. 8 is a diagram of a dual-port, shared-address bus DRAM architecture system according to the present invention;

FIG. 9 is a waveform diagram of the operation of a master and a slave port of the dual-port, shared-address bus DRAM architecture system of FIG. 8;

FIG. 10 is a schematic diagram of a slave port control circuit of the dual-port, shared-address bus DRAM architecture system of FIG. 8;

FIG. 11 is a schematic diagram of a master port control circuit of the dual-port, shared-address bus DRAM architecture system of FIG. 8; and

FIG. 12 is a schematic diagram of a priority circuit of the dual-port, shared-address bus DRAM architecture system of FIG. 8.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides a dual-port, folded-bitline DRAM architecture system which prioritizes two simultaneous access requests slated for a DRAM cell of a data array prior to performing at least one of the access requests to prevent affecting the integrity of the data while suppressing noise due to wordline-to-bitline coupling, bitline-to-bitline coupling, and bitline-to-substrate coupling. If the two access requests are read-refresh, read-read or write-refresh, where the first access request is slated through a first port and the second access request is slated through a second port of a corresponding DRAM cell of the data array, the system prioritizes the access request slated through the first port at a higher priority than the access request slated through the second port. The system thus cancels the access request slated through the second port. If the two access requests are write-read, the system prioritizes the two access requests as being equal to each other. The system then simultaneously performs the write and read access by accessing the corresponding DRAM cell through the first port to write the data while simultaneously writing the data through to an output bus, which is equivalent to a read access.

In another embodiment of the present invention, a dual-port, shared-address bus DRAM architecture system is presented which can perform two access requests in a staggered manner. That is, in a first half of a clock cycle, a DRAM cell is accessed through a first port to perform a first access request and in a second half of the clock cycle, the DRAM cell is accessed through a second port to perform a second access request.

Similarly to the folded-bitline DRAM architecture system, this system also prioritizes two simultaneous access requests slated for the DRAM cell of a data array. If the two access requests are read-refresh, read-read or write-refresh, where the first access request is slated through the first port and the second access request is slated through the second port of a corresponding DRAM cell of the data array, the system prioritizes the access request slated through the first port at a higher priority than the access request slated through the second port. The system thus cancels the access request slated through the second port.

If the two access requests are write-read or read-write, the system prioritizes the two access requests as being equal to each other. The system then simultaneously performs the write and read access or the read and write access requests by accessing the corresponding DRAM cell through the first port or second port, respectively, to write the data while simultaneously writing the data through to an output bus, which is equivalent to a read access. If the two access requests are write-write, the system prioritizes the write access request slated through the second port at a higher priority than the write access request slated through the first port. The system thus cancels the write access request slated through the first port.

This system further includes shared-address buses, thereby enabling control circuitry to be shared by both ports, since only one port of the corresponding DRAM cell can be used at a time. Hence, less control circuitry is required and all of the control circuitry can be provided at one side of the data array. Accordingly, the fabrication cost and the amount of surface area used in implementing the system are decreased.

Prioritization is realized, in order to maintain data integrity in both DRAM architecture systems, by designating one port of each DRAM cell a master port and the other port a slave port, where the access request slated through the master port has typically a higher priority than the access request slated through the slave port. Accordingly, accesses to the DRAM cell through the master port, with some exceptions, take precedence over accesses through the slave port.

Each DRAM architecture system suppresses noise due to wordline-to-bitline coupling, bitline-to-bitline coupling, and bitline-to-substrate coupling by providing at least a complementary bitline on the data array for each true bitline to form bitline pairs.

In a first section of this disclosure, the dual-port, folded-bitline DRAM architecture system is described. In a subsequent section, the dual-port, shared-address bus DRAM architecture system is described.

I. Dual-port, Folded-Bitline DRAM Architecture System

A. System Configuration and Suppressing Noise Due To The Coupling Effect

Unlike the prior art dual-port DRAM architecture syst