A four terminal full wave rectifier circuit that can be used as a pin for pin replacement for the full wave diode rectifier circuit commonly used in DC power supply circuits. Two full wave rectifier circuits that can efficiently supply the DC currents required in both discrete and integrated circuits being operated at low DC supply voltages are disclosed. Both circuits utilize two n-channel, enhancement mode Junction Field Effect Transistors (JFET) and two p-channel, enhancement mode Junction Field Effect Transistors to replace the rectifier diodes used in a conventional full wave rectifier circuit. The forward voltage drop across each JFET is considerably smaller than the forward voltage drop of a conventional rectifier. In a first configuration, the JFETs are all symmetrical about the source and drain leads. Starter devices are connected between source and drain leads and current limiting devices are in series with the gate leads. The gate leads of the JFETs are connected to the input terminals of the circuit such that a full wave rectified version of the input signal is produced at the output of the circuit. In a second configuration, two asymmetrical n-channel and two asymmetrical p-channel JFETs are used to replace the four rectifier diodes found in a conventional full wave rectifier circuit. The gate of each JFET is connected to its source lead and a full wave rectified version of the input signal is then produced at the output of this circuit.
RELATED APPLICATIONS
The following U.S. patent application Ser. No. 09/430,500, "NOVEL JFET STRUCTURE AND MANUFACTURE METHOD FOR LOW ON RESISTANCE AND LOW VOLTAGE APPLICATIONS," Ho-Yuan Yu, filed Oct. 29, 1999, and issued as U.S. Pat. No. 6,251,716 B1 on Jun. 26, 2001, is incorporated herein by reference for all purposes. This application is a continuation of U.S. patent application Ser. No. 09/741,488 filed Dec. 18, 2000. The following U.S. provisional patent application Serial No. 60/167,959, "STARTER DEVICE FOR NORMALLY OFF JFETS," Ho-Yuan Yu, filed Nov. 29, 1999, and associated utility application, entitled "STARTER DEVICE FOR NORMALLY OFF JFETS," filed Nov. 7, 2000, Ser. No. 09/708,336, by Ho-Yuan Yu, are incorporated herein by reference for all purposes.
A plain old telephone system (POTS) device, for example but not limited to, a telephone, facsimile machine, analog modem, caller identification (ID) system, speaker phone, cordless phone, etc., employs an on-board transistor-based linear polarity guard to enable decoupling of a POTS channel from one or more xDSL channels on a telephone connection (subscriber loop associated with a public service telephone network), while reducing undesirable interference, such as intermodulation distortion imposed upon the POTS and xDSL channels. Transistors associated with the polarity guard are operated in the ohmic region, or in a nonsaturated linear mode, to achieve a substantially linear transfer function through the transistors and through the overall linear polarity guard. Current that is input to the polarity guard and the voltage drop across the transistors that conduct the current in the polarity guard exhibit a substantially linear relationship, or linear VI transfer function. Hence, the VI relationship between the overall output voltage and overall input current of the polarity guard is substantially linear in the operating region of the polarity guard.
