or
Bookmark and Share
Nonvolatile semiconductor memory device having changeable spare memory address
   
Document Number
US Patent 6552950
Issued Date
April 22, 2003
Link
Inventors
Map
Abstract
A nonvolatile semiconductor memory device comprising a main memory cell array and a spare memory cell array, capable of freely accessing data in the spare memory cell array irrespective of the physical addresses of the spare memory cell array, and a method thereof are disclosed. The logical addresses of the spare memory cell array are assigned prior to the logical addresses of the main memory cell array in response to a first control signal, and data stored in the spare memory cell array is read earlier than data in the main memory cell array.
Tags:
Description:
Amusing 0%
Clever 0%
Complex 0%
Efficient 0%
Historic 0%
Important 0%
Innovative 0%
Interesting 0%
Practical 0%
Simple 0%
Number of Claims:
20
Comments:
no comments yet
Published
April 22, 2003
Application Number
09/996,240
Filed
November 28, 2001
US Classification
365/230.01   365/200 365/210 365/238.5
Int'l Classification
G11C   16/06   (20060101)   G11C   16/08   (20060101)  
Examiner
Assistant Examiner
Attorney/Law Firm
Priority Data
Jun 11, 2001 [KR] 2001-32468
USPTO Field of Search
365/185.17   365/200   365/210   365/221   365/230.01   365/230.06   365/235   365/238.5   365/230.09   365/154   365/191   365/236  
Related Patents
7085167 - Methods for programming user data and confirmation information in nonvolatile memory devices - Owned by Samsung Electronics Co., ltd. (KR)

Method of programming nonvolatile memory devices are provided in which data is programmed into a first plurality of memory cells of the nonvolatile memory device. At the same time associated programming confirmation information is programmed into at least one second memory cell of the nonvolatile memory device. Then, a determination is made as to whether the data was correctly programmed into the first plurality of memory cells based on an evaluation of (1) the threshold voltage distributions of at least some of the first plurality of memory cells and (2) the threshold voltage distribution of the at least one second memory cell. Methods of resuming a data programming operation after an interruption such as a loss of power are also provided.

Claims
Description
About| FAQs| Terms & Disclaimer| Link to Us| Contact Us