An apparatus and method is disclosed for providing a phase locked loop clock divider circuit utilizing a high speed linear feedback shift register with a two stage pipeline in its feedback path. A plurality of "pre-load" flip flop (PLFF) circuits and multiplexers are coupled to a plurality of linear feedback shift register (LFSR) flip flop circuits and multiplexers. The PLFF circuits hold pre-calculated initial LFSR sequence values to be loaded into the LFSR flip flop circuits. The load enable signal to the PLFF multiplexers and to the LFSR multiplexers is low for three successive input clock cycles. The present invention is capable of operating at high frequencies due to a shortened timing critical feedback path.
CROSS REFERENCE TO RELATED APPLICATION
This patent application is related to and claims priority as a continuation-in-part of U.S. patent application Ser. No. 09/960,590 entitled PHASE LOCKED LOOP CLOCK DIVIDER UTILIZING A HIGH SPEED PROGRAMMABLE LINEAR FEEDBACK SHIFT REGISTER filed on Sep. 21, 2001, now U.S. Pat. No. 6,424,691. U.S. patent application Ser. No. 09/960,590 is commonly assigned to the assignee of the present patent application. The disclosures of U.S. patent application Ser. No. 09/960,590 are hereby incorporated by reference in the present patent application as if fully set forth herein.
The shift register, which is an n-th shift register of a shift register chain, includes a first multiplexer, a second multiplexer, and a latch block, wherein n is a positive integer. The first multiplexer selects one of output data of the (n-1)-th shift register or output data of the (n+1)-th shift register and outputs the selected data to be used as a reset signal in the latch block. The second multiplexer selects one of the output data of the (n-1)-th shift register or the output data of the (n+1)-th shift register and outputs the selected data to be used as input data of the latch block. The latch block stores the output data of the second multiplexer in response to the clock control signal, the inverted clock control signal and the reset voltage, and outputs the stored data.
