A split sparse directory for a distributed shared memory multiprocessor system with multiple nodes, each node including a plurality of processors, each processor having an associated cache. The split sparse directory is in a memory subsystem which includes a coherence controller, a temporary state buffer and an external directory. The split sparse directory stores information concerning the cache lines in the node, with the temporary state buffer holding state information about transient cache lines and the external directory holding state information about non-transient cache lines.
This application claims the benefit of U.S. Provisional Application No. 60/084,795, filed on May 8, 1998.
CROSS-REFERENCE TO CO-PENDING APPLICATIONS
This application is related to U.S. patent application Ser. No. 09/041,568, entitled "Cache Coherence Unit for Interconnecting Multiprocessor Nodes Having Pipelined Snoopy Protocol," filed on Mar. 12, 1998; U.S. Pat. No. 6,212,610, entitled "Memory Protection Mechanism for a Distributed Shared Memory Multiprocessor with Integrated Message Passing Support," issued on Apr. 3, 2001; and U.S. Pat. No. 6,209,064, entitled "Cache Coherence Unit with Integrated Message Passing and Memory Protection for a Distributed, Shared Memory Multiprocessor System," issued on Mar. 27, 2001; which are hereby incorporated by reference.
A memory device and method which provide at least one memory segment. The memory segment includes at least one first portion which is configured to store data. The memory segment also includes at least one second portion associated with the first portion, and which is configured to store directory information for at least one cache line thereon.
A dual system shared cache directory structure for a cache memory performs the role of an inclusive shared system cache, i.e., data, and system control, i.e., coherency. The system includes two separate system cache directories in the shared system cache. The two separate cache directories are substantially equal in size and collectively large enough to contain all of the processor cache directory entries, but with only one of these separate cache directories hosting system-cache data to back the most recent fraction of data accessed by the processors. The other cache directory retains only addresses, including addresses of lines LRUed out from the first cache directory and the identity of the processor using the data. Thus by this expedient, only the directory known to be backed by system cached data will be evaluated for system cache memory data.
A method and structure for an emulation system comprises of a plurality of field programmable gate arrays adapted to emulate nodes of a multi-node shared memory system, a plurality of cache directories, each connected to one of the arrays, and a plurality of global coherence directories, each connected to one of the arrays. Each of the global coherence directories maintain information on all memory lines remotely cached by each of the cache directories.
A method, apparatus, and computer implemented instructions for managing a plurality of caches of data, wherein the data processing system includes a plurality of independent computers. In response to initiating a read operation to read data on a data block, an indication is posted on a directory of data blocks identifying the computer that now holds a copy of that block and a location in the memory of that computer where a flag associated with that block is held. Then in response to initiating a write operation on that data block, messages are sent to all the computers holding that block which resets the said flag, thus informing each computer that the data in that block is no longer valid. These messages are sent using means that perform that flag reset without, in the preferred embodiment, any overhead of interruption of processing on the computers where the flags reside.
Cache management strategies are described for retrieving information from a storage medium, such as an optical disc, using a cache memory including multiple cache segments. A first group of cache segments can be devoted to handling the streaming transfer of a first type of information, and a second group of cache segments can be devoted to handling the bulk transfer of a second type of information. A host system can provide hinting information that identifies which group of cache segments that a particular read request targets. A circular wrap-around fill strategy can be used to iteratively supply new information to the cache segments upon cache hits by performing pre-fetching. Various eviction algorithms can be used to select a cache segment for flushing and refilling upon a cache miss, such as a least recently used (LRU) algorithm or a least frequently used (LFU) algorithm.
