An insulated gate bipolar transistor (IGBT) and a method for manufacturing the same is provided. This method is capable of preventing a latch-up and improving a short current characteristic. In the IGBT, a second conductive type semiconductor layer is formed over a semiconductor substrate. A first conductive type well is then formed beneath the surface of the semiconductor layer, and a second conductive type source region doped with a high concentration is formed in the well. Also, a gate electrode is formed over the semiconductor layer, but so as not to contact the source region in a region in which a contact between the source region and a cathode electrode is formed. Also, the IGBT further includes an impurity region for controlling latch-up, the impurity region being extended to a part of the semiconductor layer via the well.
A semiconductor device is disclosed and includes a drain region of a first conductivity type, having a first major surface. Diffused into the drain region is a body region of a second conductivity type. A source region is diffused in the body region and it has a general polygonal shape when viewed at the first major surface with two notches directed towards the center of the source region from opposite sides. The body region is accessible through the notches. An oxide layer covers the source and body regions except for a contact opening position over the source region between the two notches exposing only that portion of the source region that is between the two notches and at least a portion of the accessible body region in each of the two notches to facilitate a source contact.
A semiconductor device capable of lowering the ON voltage by decreasing the area of the invalid region compared to that of prior art yet maintaining the ability for suppressing the latch-up comparable to that of the conventional IGBTS. The semiconductor device comprises a semiconductor layer of a first conductivity type, a collector layer of a second conductivity type formed on one surface of the semiconductor layer, a base layer of the second conductivity type formed on the other surface of the semiconductor layer, and an emitter layer of the first conductivity type formed in the base layer, wherein the emitter layer having the shape of a ladder being constituted by two crossbeams and cleats formed between the crossbeams, the cleat being provided even between facing end portions of the two crossbeams.
