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Passivation structure for an integrated circuit
   
Document Number
US Patent 6566737
Issued Date
May 20, 2003
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Abstract
A novel passivation structure and its method of fabrication. According to the present invention a first dielectric layer is formed upon a conductive layer formed over a substrate. The first dielectric layer and the conductive layer are then patterned into a first dielectric capped interconnect and a dielectric capped bond pad. Next, a second dielectric layer is formed over and between the dielectric capped interconnect and the dielectric capped bond pad. The top portion of the second dielectric layer is removed so as to expose the dielectric capped bond pad and the dielectric capped interconnect. A third dielectric layer is then formed over the exposed dielectric capped bond pad and the exposed dielectric capped interconnect and over the second dielectric.
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Number of Claims:
17
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Owner
Intel Corporation (Santa Clara, CA)
Published
May 20, 2003
Application Number
09/115,418
Filed
July 14, 1998
US Classification
257/635   257/784 257/E21.279 257/E21.293 257/E21.502 257/E23.132 257/E23.167
Int'l Classification
H01L   23/532   (20060101)   H01L   21/02   (20060101)   H01L   23/52   (20060101)   H01L   21/56   (20060101)   H01L   23/31   (20060101)   H01L   23/28   (20060101)   H01L   21/316   (20060101)   H01L   21/318   (20060101)  
Examiner
Assistant Examiner
Parent Case
This is a divisional application of Ser. No. 09/001,551 filed on Dec. 31, 1997, now U.S. Pat. No. 6,143,638.
USPTO Field of Search
257/635   257/636   257/637   257/638   257/639   257/640   257/641   257/642   257/643   257/644   257/645   257/635   257/636   257/637   257/638   257/639   257/640   257/641   257/642   257/643   257/644   257/645   257/635   257/636   257/637   257/638   257/639   257/640   257/641   257/642   257/643   257/644   257/645   438/612   438/633  
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A structure and a method for forming the same. The method includes (a) providing a structure which includes (i) a dielectric layer, (ii) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface, (iii) a first passivation layer on the dielectric layer top surface and on the electrically conducting bond pad, wherein the first passivation layer comprises a first hole directly above the electrically conducting bond pad, and (iv) an electrically conducting solder bump filling the first hole and electrically coupled to the electrically conducting bond pad; and (b) forming a second passivation layer on the first passivation layer, wherein second passivation layer is in direct physical contact with the electrically conducting solder bump, and wherein the electrically conducting solder bump is exposed to a surrounding ambient immediately after said forming the second passivation layer is performed.

Claims
Description
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