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STATEMENT OF FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates in general to computers and, more particularly, to computer memory modules.
2. Description of the Related Art
Over the last few years, the operation of the personal computer has become more oriented toward multimedia operation. Multimedia computers typically include a mass storage device with a replaceable medium, such as a CD-ROM (compact disk read
only memory) or a DVD (digital versatile disk), a sound card with a FM synthesis or wave table generation processor, real-time video capabilities and three dimensional graphics. Other multimedia capabilities, such as speech synthesis and voice
recognition, are becoming more mainstream as the power of the computers increase.
Multimedia capabilities such as sound, video, fax, modem, compression and decompression, however, are resource intensive. Some features are bandwidth limited, meaning that the features cannot be expanded without increasing the bandwidth of the
system buses. In a typical IBM-compatible PC, the ISA (industry standard architecture) bus runs at eight megahertz (16 bits) while the PCI (Peripheral Connect Interface) bus runs at thirty-three megahertz (32 bits). Other features are processor
limited. In a multitasking computer system, the main processor can be responsible for a number of activities. Therefore, multimedia features which require a large number of processor instruction cycles can slow down the system or not execute properly.
Still other multimedia features are memory limited. These features require a large amount of memory in order to execute. Large memories lead to increased system cost.
For example, modem features like V.34bis are primarily processor limited. Wavetable synthesis requires large amounts of memory and is memory-limited. Decompression feature like MPEG2 is compute-limited as well as bandwidth limited. With
increasing clock-speeds of Intel CPUs, some of these can be executed on the host CPU. But this loads the host CPU with fewer MIPS (million instructions per second) available for the user application. Increased clock speeds also lead to increased power
consumption and reduced battery life.
One popular approach is to provide these functions in a desktop computer using multiple add-in ISA or local bus cards. These add-in cards are host dependent and cannot be used on multiple platforms. For example, an ISA card cannot work on a Sun
workstation or a Macintosh. Notebook computers, palmtops and PDAs (personal digital assistants) have no space for such ISA cards. And they all suffer from the classic Von Neumann bottleneck--the CPU-Memory bandwidth limitation.
Processor technology has focused on improving raw processing speed. As an example, the instruction cycle time of a recent digital signal processor design in the TMS320 family, by Texas Instruments Incorporated of Dallas, Tex., is 5 ns
(nanoseconds), as compared to the cycle time of 200 ns in the first generation. As long as the computations are on-chip, these devices provide adequate throughput. But several applications in speech, signal and image processing are memory intensive and
the gain in raw processing speed is lost when the processor has to fetch and process data from slower off-chip memories. The combined effect of decreasing cycle time of processors and increasing density of memory devices is further aggravating the
CPU-to-memory bandwidth--a paramount issue in computer system design.
As computers evolve from desktop size to laptop, notebook and palmtop sizes, form factor and power consumption become critical. Laptops are expected to have the capability of a desktop as users demand more functionality.
Multiprocessing promises great potential for increasing the throughput of systems as the limits of decreasing the cycle time of uniprocessor systems are approached. But multiprocessing has not yet proliferated, primarily because of the
"processor-driven" approaches and the difficulty in designing systems, developing communication protocols, and designing software support routines. Application partitioning is a major problem because it requires a detailed understanding of the
application that is being accelerated. Software development methodologies and partitioning tools are still in their infancy. In addition, there is no standard way of connecting two or more processors.
Accordingly, a need has arisen for a method and apparatus for providing flexible, compatible processing for multimedia and other resource intensive features.
BRIEF SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, the present invention provides a memory module comprising a semiconductor memory and one or more processors coupled to the semiconductor memory on an integrated module. Circuitry on the
integrated module provides communications between system processing circuitry and the processor, such that said system processing circuitry can access the semiconductor memory as main memory and can instruct the processor to transform data and store
transformed data in said semiconductor memory for access by the system processing circuitry.
The invention provides significant advantages over the prior art. Adding a digital signal processor to a computer system to enable enhanced functions is as easy as expanding the memory of a MPU (main processing unit). The memory module can use
a form factor of the type standardized by organizations like IEEE, JEDEC, and so on, such as a SIMM (single in-line memory module) or DEMM (dual in-line memory module) form factor.
Different applications may be downloaded by the MPU to the memory module for local execution. The memory module therefore supports multiple functionality, i.e., downloadable, multiple functions under software control of the MPU.
The DSP/memory module offers the highest possible bandwidth between the MPU and coprocessor at any given time and technology. The DSP/memory module is both bus-independent, and host-independent, for use with PCs (personal computers), PDAs
(personal digital assistants), workstations and other computer systems.
The DSP/memory module reduces system cost by sharing system memory over a number of multimedia functions.
The module provides a framework for easily scaling up the processing power of a computer system; an existing single processor system can be transformed into a scaleable, multiprocessing system simply by adding a memory module
Users do not have to change their product platforms in order to get/offer new, value-added functions. Adding the DSP/memory module and software can allow users to increase the capability of their computers.
In accordance with other embodiments of the present invention, implementation of the memory module with the interrupt request, IREQ, and WAIT signals are described further in this application. Six options are presented in accordance with other
embodiments describing how to implement these signals (including their timing and relation to the host memory controller).
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIG. 1 illustrates a prior art computer architecture;
FIG. 2 illustrates a DSP/memory module;
FIG. 3 illustrates the organization of memory space between the system MPU and the DSP on the DSP/memory module;
FIGS. 4a, 4b, 4c, 4d illustrate definitions of control words used to control the operation of the DSP/memory module;
FIG. 5 illustrates a flow chart describing the operation of a hunting protocol for determining whether a DSP/memory module is located in the main memory of a computer;
FIG. 6 illustrates a memory map in standard mode;
FIG. 7 illustrates a memory map in smart-local mode;
FIG. 8 illustrates a memory map in smart-shared mode;
FIG. 9 illustrates a first embodiment of the DSP/memory module;
FIG. 10 illustrates a second embodiment of the DSP/memory module;
FIG. 11 illustrates a third embodiment of the DSP/memory module;
FIG. 12 illustrates a DSP/memory module in a computer system using an analog front end directly connected to the module;
FIG. 13 illustrates a DSP/memory module in a computer system using an analog front end coupled to the memory module via a local bus card;
FIG. 14 illustrates the memory module(s) to host controller block diagram as discussed in "IMPLEMENTATION OF IREQ AND WAIT SIGNALS: OPTION 1";
FIG. 15 illustrates the timing for the WAIT signal for FPM or EDO DRAM as discussed in "IMPLEMENTATION OF IREQ AND WAIT SIGNALS: OPTION 1";
FIG. 16 illustrates the timing for the WAIT signal for DDR-S/S DRAM, eligibility option 1, as discussed in "IMPLEMENTATION OF IREQ AND WAIT SIGNALS: OPTION 1";
FIG. 17 illustrates the timing for the WAIT signal for DDR-S/S DRAM, eligibility option 2, as discussed in "IMPLEMENTATION OF IREQ AND WAIT SIGNALS: OPTION 1";
FIG. 18 illustrates the timing for the WAIT signal for DDR-S/S DRAM, eligibility option 3, as discussed in "IMPLEMENTATION OF IREQ AND WAIT SIGNALS: OPTION 1";
FIG. 19 illustrates the memory module(s) to host controller block diagram as discussed in "IMPLEMENTATION OF IREQ AND WAIT SIGNALS: OPTION 2";
FIG. 20 illustrates the timing for the WAIT signal for FPM or EDO DRAM as discussed in "IMPLEMENTATION OF IREQ AND WAIT SIGNALS: OPTION 2";
FIG. 21 illustrates the timing for the WAIT signal for DDR-S/S DRAM, eligibility option 1, as discussed in "IMPLEMENTATION OF IREQ AND WAIT SIGNALS: OPTION 2";
FIG. 22 illustrates the timing for the WAIT signal for DDR-S/S DRAM, eligibility option 2, as discussed in "IMPLEMENTATION OF IREQ AND WAIT SIGNALS: OPTION 2";
FIG. 23 illustrates the timing for the WAIT signal for DDR-S/S DRAM, eligibility option 3, as discussed in "IMPLEMENTATION OF IREQ AND WAIT SIGNALS: OPTION 2";
FIG. 24 illustrates the memory module(s) to host controller block diagram as discussed in "IMPLEMENTATION OF IREQ AND WAIT SIGNALS: OPTION 3";
FIG. 25 illustrates the timing for the WAIT and IREQ signals for FPM or EDO DRAM as discussed in "IMPLEMENTATION OF IREQ AND WAIT SIGNALS: OPTION 3";
FIG. 26 illustrates the timing for the WAIT and IREQ signals for DDR-S/S DRAM, eligibility option 1, as discussed in "IMPLEMENTATION OF IREQ AND WAIT SIGNALS: OPTION 3";
FIG. 27 illustrates the timing for the WAIT and IREQ signals for DDR-S/S DRAM, eligibility option 2, as discussed in "IMPLEMENTATION OF IREQ AND WAIT SIGNALS: OPTION 3";
FIG. 28 illustrates the timing for the WAIT and IREQ signals for DDR-S/S DRAM, eligibility option 3, as discussed in "IMPLEMENTATION OF IREQ AND WAIT SIGNALS: OPTION 3";
FIG. 29 illustrates the memory module(s) to host controller block diagram as discussed in "IMPLEMENTATION OF IREQ AND WAIT SIGNALS: OPTION 4";
FIG. 30 illustrates the memory module(s) to host controller block diagram as discussed in "IMPLEMENTATION OF IREQ AND WAIT SIGNALS: OPTION 5";
FIG. 31 illustrates the timing for the WAIT and IREQ signals for DDR-S/S DRAM, eligibility option 1, as discussed in "IMPLEMENTATION OF IREQ AND WAIT SIGNALS: OPTION 5";
FIG. 32 illustrates the timing for the WAIT and IREQ signals for DDR-S/S DRAM, eligibility option 2, as discussed in "IMPLEMENTATION OF IREQ AND WAIT SIGNALS: OPTION 5";
FIG. 33 illustrates the timing for the WAIT and IREQ signals for DDR-S/S DRAM, eligibility option 3, as discussed in "IMPLEMENTATION OF IREQ AND WAIT SIGNALS: OPTION 5"; and
FIG. 34 illustrates a possible solution for module-to-module communication via a 2 wire bus.
DETAILED DESCRIPTION OF THE INVENTION
The present invention is best understood in relation to FIGS. 1-12 of the drawings, like numerals being used for like elements of the various drawings.
FIG. 1 illustrates a prior art computer system 10. A main processor (hereinafter MPU) 12 communicates with other electronic devices over one or more paths. In FIG. 1, the MPU 12 is coupled to a memory management unit (MMU) 14, a PCI bridge 16,
an AT interface unit 18 and a PCMCIA (Personal Computer Memory Card International Association) bridge 20. The MMU 14 couples the MPU 12 to main memory 22 via a memory bus 24, which is typically a vendor specified bus. The main memory 22 is typically
formed of a plurality of memory modules 26 packaged in a standard form factor. The most popular form factor is currently the SIMM module, although DIMM modules are gaining in popularity.
The PCI Bridge 16 couples the MPU 12 to a PCI local bus 28. The PCI local bus provides slots for one or more peripheral cards 30. Because the PCI bus is faster than the AT bus, it is generally used for higher speed peripherals such as the
video/graphics card.
The AT interface unit 18 couples the MPU 12 with the AT bus 32 (also known as the ISA--industry standard architecture--bus). The AT bus 32 can receive one or more peripheral cards 34. The PCMCIA bridge 20 is coupled to the AT interface unit and
provides a PCMCIA bus 36 to support externally replaceable peripherals 38 (also known under the name "PC Cards") which are commonly used in notebook computers.
A card having one or more processors can be added to an existing PC platform via the ISA bus 32 or, more recently, the PCI bus 28. The ISA bus 32 was developed several years ago and many popular peripheral cards subscribe to this standard.
However, the bandwidth between the MPU and a processor on a ISA card is limited to 8 MHz*16 bits per second. There are several sound applications today that cannot run due to this bandwidth limitation. Later, the. PCI bus was proposed as a standard
bus; its bandwidth is limited to 33 MHz*32 bits per second. In either case, the technology has developed faster than the bus technology.
In order to reduce bus traffic somewhat, MMX technology is currently available. While MMX technology allows the MPU to perform some multimedia functions through an enhanced instruction set, it has significant disadvantages. Data must be moved
from main memory to the MPU 12 for processing. This results in significant bus traffic, loads the MPU 12 and demands faster and faster processor speeds. For example, it is estimated that MPEG2 video and audio decoding in real-time at a rate of thirty
frames per second requires a 225 MHz Pentium processor. In order to provide the MMX instructions, the MPU 12 must switch between floating point mode and fixed point mode. There is a significant overhead in switching between modes and switching can be
frequent in multitasking systems where both floating point applications (such as a spreadsheet) and fixed point applications are being used.
FIG. 2 illustrates a DSP/memory module which provides a solution to many of the problems associated with the architecture shown in FIG. 1, using a concept referred to herein as "Basava" technology. The DSP/memory module 40 includes one or more
memory circuits 42 and DSP circuitry 44 disposed on a substrate 46. A plurality of contacts 48 are formed on substrate 46 to electrically connect the DSP/memory module 40 to the system board which houses the MPU 12. In the preferred embodiment, the
DSP/memory module 40 is inserted into a standard memory slot, such as a SIMM slot or a DIMM slot.
In operation, the DSP/memory module 40 is placed onto the system board of the computer in a slot connected to the memory bus 24. The DSP functions of the DSP/memory module 40 are initially transparent to the MPU 12; the DSP/memory module 40
operates as a standard memory module 26 until the DSP features are enabled. Once enabled (discussed in greater detail hereinbelow), the MPU 12 can control the DSP circuitry 44 through a plurality of control registers and pass data to and from the DSP
circuitry 44 using some or all of the memory circuits 42.
Many applications in digital signal processing, speech, and image processing are structured and lend themselves to be partitioned and concurrently executed. With adequate on-chip memory, several self-contained tasks can be executed in parallel.
Typically, there are small routines or operations that are applied to a very large set of data. For example, in speech or image recognition, the unknown input vector is compared against several stored reference vectors. Typically, a Euclidean distance
is used as a similarity measure between the unknown vector and the known reference vector. This calculation involves fetching the reference vectors from memory to the MPU 12 where the unknown input vector is kept, performing the Euclidean distance
calculation, and writing the computed result back to memory. Moving the large number of reference vectors to the MPU 12 increases the traffic of data on the bus. However, using the DSP/memory module 40, the input vector can be moved to the memory
storing the reference vectors, previously loaded on the DSP/memory module 40, performing the Euclidean calculation locally, and storing the results locally. Now, the MPU 12 need only fetch the results from the DSP/memory module 40. This leads to
several benefits. First, the data traffic on the buses is reduced since the MPU 12 must read only the compared results. Second, the MPU is free to perform other tasks while the DSP/memory module 40 performs the cycle intensive Euclidean computation.
Third, due to reduced bus traffic, power consumption is reduced leading to increased battery life--an important feature for portable system users.
With the density of DRAM increasing, memory intensive applications, such as a voice dialing application, which typically requires a megabit of memory, can easily be supported on the DSP/memory module 40.
FIG. 3 illustrates a diagram showing the interaction between the MPU 12, memory circuits 42 and the DSP circuitry 44. The main memory of the computer system is generally divided into "banks," with each bank 50 comprising one or more memory
modules. In the computer system of FIG. 3, four banks are shown, BANK0, BANK1, BANK2 AND BANK3. BANK3 contains the DSP/memory module 40 (although any bank could contain the module); in another instance, all the banks 50 may contain a DSP/memory module
40.
Each bank 50 has an associated address space, through which the MPU 12 addresses the memory (via the MMU 14). For a Pentium type processor, the address range is from 0 to 4 gigabytes Typically, the actual memory addresses are in a much smaller
range, for example, between 0 and 64 megabytes. Within the address space associated with BANK3, a certain range of addresses are allocated for control registers 52 associated with the DSP circuitry 44, used when the DSP circuitry is enabled. These
control registers are described in further detail hereinbelow. Further, a portion of the memory can be designated as shared memory 54, i.e., for use with both the MPU 12 and the DSP 56 (multiple DSPs could also be used on a single module). DSP 56 is
typically a digital signal processor, but could alternatively be any type of programmable processor. In addition to the main memory, the DSP circuitry 44 also has a local memory 58 (preferably a static random access memory) for temporary storage of
information.
When the DSP circuitry 44 is not enabled ("standard mode"), the DSP/memory module 40 operates as a standard memory module. In the diagram of FIG. 3, the MPU 12 would have sole access to the entire memory address space of BANK3, just as it would
any other memory bank 50. When the DSP/memory module 40 has its DSP circuitry 44 enabled ("smart mode"), the MPU 12 can write to the control registers 52 to control the DSP functions and can transfer data to and from the DSP circuitry 44 via the shared
memory.
In a third mode, configuration mode, the MPU 12 can access the control registers 52 and local memory 54 present on the DSP/memory module 40, via the Index and Data registers that are in the memory space of the DSP/memory module 40. On powerup,
these control registers 52 are located at the base of the address space of the DSP/memory module 40. The intent of the configuration mode is two fold. First, configuration mode enables the MPU 12 to read specific information regarding the DSP/memory
module 40, referred to as the Module Information Structure (MIS). MIS contains information regarding the size of memory available on the DSP/memory module 40, size of the local memories, and the type of processor(s) available. The MPU 12 accesses this
MIS and stores this information in its registry for future reference and actions. The MIS is typically stored in slow memories like ROM and the MPU 12 must poll the status bits in the DSPSR register before reading from the data register. The specific
bits are explained further below. Second, the configuration mode is used to relocate the base address of the control registers 52 and the shared memory 54 to a desired address location within the boundary of the module. Note that the default base
address is zero, i.e., the control registers are located at the starting address of the bank 50.
The following provides a preferred procedure for switching between modes. To switch from standard mode to configuration mode; the MPU 12 writes a signature pattern, times, in succession, to the signature register (SIGR) located in its address
space. This signature pattern is written a certain number of times, without doing any other accesses. For example, a signature pattern, "A320", could be written four times in succession to the SIGR register to enter configuration mode.
To switch from configuration mode to standard mode, the MPU 12 writes to the DSPLOC register the "relocation address" to which it wishes to relocate the control register's base address to be relocated. If it does not wish to relocate the control
registers, a "0" is written to the DSPLOC registers. After writing the relocation address, the MPU 12 writes the signature pattern to the SIGR/Index register.
To switch from standard mode to smart mode, the MPU 12 writes a signature pattern (n+1) times, in succession, to the signature register (SIGR) located in its address space. This signature pattern is written a certain number of times, without
doing any other accesses. For example, the signature pattern, "A320", is written five times in succession to the SIGR register.
If for any reason, the computer is reset, or shut-down, the driver in the OS will switch the module back to the standard mode before allowing the computer to shutdown. Alternatively, on power-up, the boot sequence might always force the module
to be in standard mode.
Control Registers
Control of the module's operating mode is accomplished via the signature, control, status, and communication registers defined in the module controller, shown in connection with FIGS. 9-11. Some of these are accessible only by the MPU 12, some
only by the DSP 56, and some by both MPU 12 and DSP 56. Some of these registers are mapped in the memory space of the MPU 12 and I/O space of the DSP 56. Note that for both MPU 12 and DSP, some of these registers are "Reserved" as marked. In the
standard mode, only the Signature Register (SIGR) is accessible to the MPU 12. Other registers exist only when the DSP/memory module 40 is in the configuration or smart mode of operation.
Initially, these registers are mapped into the first 32 bytes of the associated bank 50.
TABLE I Control Registers in Standard Mode Register Memory Address Default Access Name MPU Memory DSP I/O Space Value MPU DSP SIGR 0000h -- XXXXh R/W --
TABLE II Control Registers in Configuration Mode or Smart Mode Register Memory Address Default Access Name MPU Memory DSP I/O Space Value MPU DSP SIGR/ 0000h -- XXXXh R/W -- INDEX DATA 0007h -- XXXXh R/W --
TABLE III Control Registers in Configuration and Smart Modes, accessible via Index & Data Registers. Register Memory Address Default Access Name MPU Memory DSP I/O Space Value MPU DSP DSPLOC Via Index & -- 0000h R/W -- Data registers DSCR
Via Index & -- XXXXh R/W -- Data registers DSPSR Via Index & -- XXXXh R -- Data registers DSPTxD Via Index & 0050h 0000h R W Data registers DSPRxD Via Index & 0051h 0000h W R Data registers LM_RW.sub.-- Via Index & -- 0000h R/W -- ADDR Data
registers LM_RW.sub.-- Via Index & -- 0000h R/W -- DATA Data registers LM_AD.sub.-- Via Index & -- 0000h R/W -- OFFSET Data registers
SIGR Register
The Signature (SIGR) register is defined only in the standard mode. The DSP/memory module 40 monitors all MPU writes to this location for valid signature pattern (while it writes to the standard memory typically available on the module). When
the module operates in the configuration mode, this register is redefined as the Index Register. The module still monitors for a write of a signature pattern (for example, "A320") and if this occurs after a write to the DSPLOC register, then the module
is switched back to the Standard mode. During the smart mode, this register is redefined as the Index Register.
Index Register
The Index Register which is available in the configuration and smart modes enables access to other registers like DSPCR, etc. The MPU 12 must write the address of the control registers that it wishes to access to this register.
Data Register
The Data register is a read/write register available in the Configuration and Smart modes. The MPU 12 writes the data to this register which is transferred by the module to the appropriate control register 52 whose address has been previously
setup in the Index register.
The Index and Data registers have been defined to facilitate ease of hardware circuit implementation; since meeting the tight memory-access timings in Fast-Page mode are difficult to meet. Ideally all control registers 52 could be directly
accessible by the host MPU 12.
DSPLOC Register
The DSPLOC is a 16-bit RJW register that allows the MPU 12 to relocate the base of the control registers 52 to another address in the MPU's address space, but still within the boundary of the module's address limits.
DSP Control Register (DSPCR)
The DSPCR, shown in FIG. 4a, is a 16 bit R/W register used to control DSP operation, interrupt of the MPU, memory bus arbitration, standard-smart mode switching, and level interrupt clear. Definition of individual bits are as follows.
Note that with the DSP specific bits, though some protections have been included, the operation is not fully automated. Thus, the user must program DSPCR while taking into consideration DSP operation. The DSPCR bits are explained in the
following Table IV.
TABLE IV DSPCR Operation Bit0 DSP RESET: Writing a 0 to this bit resets the DSP 56. The MPU 12 must set this bit to 1 to start DSP operation. When doing this, at least two writes to DSPCR should occur. The first should write the
appropriate configuration with RESET=0. The second write should do the same with RESET=1. The Default value is 0. Bit1 SHARED MEM IN USE: This is a semaphore used in arbitrating access to shared memory. Bit2 DSP CLKMD1: This bit selects the DSP
master clock source and corresponds to the DSP CLKMD1 bit only (since CLKMD0 is tied low). The DSP RESET bit must be 0 when this bit is changed. When this bit is set to 0, CLKMD1=0 and the DSP is in divide-by-two mode so DSP's clock input is driven
by the clock divider output (in SYSCFG) at a minimum instruction cycle of 100 ns. When this bit is set to 1, CLKMD1=1 and the DSP is in multiply-by-two mode so the DSP's clock input is the oscillator output with an instruction cycle time of 25 ns.
The DSP should not be taken out of reset on the same write cycle that the clock is turned on; instead, two writes should be used. Note that in the 25 ns mode, the clock can only be turned off if the part is in IDLE2. The default is value for this
bit is 0. Bit3 DSP MP/-MC: This bit corresponds to the DSP MP/-MC pin. When it equals 1 and the DSP is taken out of reset, the DSP is in microprocessor mode and begins running out of external memory. Setting this bit to 0 sets the DSP MP/-MC pin=0.
thus allowing the part to be bootloaded when the DSP is taken out of reset. This means the DSP is brought up in microcomputer mode that causes the part to bootload code in from global data memory. The DSP can only bootload out of page 0 of global
data memory. The default value is 1. After bootload, this bit must be set to 1. The MP/- MC is multiplexed with -INT1 pin and this must be done for DSP interrupts to work correctly. Bit4 TXINTEN: This bit is used by the MPU 12 to receive an interrupt
when DSPTXD is written to by the DSP. When TXINTEN is set (1), TXFULL condition in the DSPSR will generate an interrupt to the MPU 12 allowing interrupt driven communications with the DSP. Writing a 0 will disable, but not clear the interrupt. The
default value of this bit is 0. Bit5 RXINTEN: This bit is used by the MPU 12 to receive an interrupt when DSPRXD is read by the DSP. When RXINTEN is set (1), RXEMPTY condition in the DSPSR will generate an interrupt to the MPU 12 allowing interrupt
driven communications with the DSP. Writing a 0 will disable, but not clear the interrupt. The default value of this bit is 0. Bit6RESERVED: Local Memory Read/Write control flag. 0=READ; 1=WRITE; Default=0 Bit7 DEVBUSYINTEN: This bit is used by the
MPU 12 to receive an interrupt when MPU memory access timeout occurs. When DEVBUSYINTEN is set (1), DEVBUSYINT condition in the DSPSR will generate an interrupt to the MPU 12. This is an error condition and described. Writing a 0 will clear the
interrupt. The default value for this bit is 0. Bit8 MANUAL HOLD: Writing a 0 to this bit will set the -HOLD line to the DSP to 0. This keeps the DSP off the memory bus so that the MPU 12 may have uncontested, fully optimized access to the
memory/DSP bus with no arbitration delay. The actual value of -HOLDA may be polled in DSPSR. This mode is good for block accesses of data to the memory/DSP bus. Default value for this bit is 1. (Note that when the DSP/memory module 40 is in standard
mode, -HOLD=0.) Bit10-9 LM_ADR_CTRL: Local Memory address modification control after access to DATA register; 00=No change; 01=increment LM_RW_ADDR register by +1; 10=decrement LM_RW_ADDR register by -1; 11=use value in LM_AD_OFFSET to modify
LM_RW_ADDR register. The default value is 00. Bit 11 MAXOD (Maximum Overdrive): Writing a 0 to this bit causes any MPU 12 access to the module controller to -HOLD the DSP. This will of course slow down DSP operation, but guarantee no bus
arbitration conflicts. Writing a 1 to this bit turns on the bus arbitration optimization that allows DSP and MPU 12 to access the module controller concurrently. When this bit is active any access to the module controller will NOT cause the DSP -HOLD
signal to be applied low. The default value for this bit is 0. Bit 12 IREQSERV (IREQ Service): In the case of either pulse or level interrupts, this bit must be cleared AND primed. This means that when MPU 12 is servicing an interrupt, a 1 must be
written to this bit to clear it. And then a 0 MUST be written to this bit to prime it for the next interrupt. Otherwise-IREQ will not toggle again. This puts the time between IREQ's (and pulsed interrupts will pulse only once) fully in control of
the MPU 12 programmer. Bit14-13 LM_SPACE_SELECT: Local Memory space select. These two bits specify which space in the local memory space of the module should be selected. At present, Module Information Space(MIS). DSP Program Space(DSP_PM). and DSP
Data Space(DSP_DM) are supported. 00=MIS: 01=DSP_PM:10=DSP_DM:11=not defined. Default is 00. Bit 15 MODCTL: When the MPU 12 switches the DSP/memory module 40 to smart mode by writing the signature to SIGR. this bit will be set to 1. (Note that it
will not be latched until a write occurs to DSPCR). Writing a 0 to this bit will reset the smart mode and force the DSP/memory module 40 to the standard mode. When writing to this register, always be sure to write 1 to this bit or that DSP/memory
module 40 will switch to standard mode. Also note that writing 0 will not take the DSP/memory module 40 out of smart mode if MODE bit in the COR's is 1. Default value for this bit is 0.
DSP Status Register
The DSPSR, shown in FIG. 4b, is a read-only, 16-bit register. It is used to monitor DSP operation, module interrupt of the MPU 12, and memory/DSP bus arbitration. Definition of individual bits are as follows in Table V:
TABLE V DSPCR Bit Operation Bit1-0 RESERVED: These bits are reserved and may reflect any value that has no relevance to the operation of the DSP/memory module 40. Bit2 DSP CLKMD1: This bit indicates the value of the DSP CLKMD1 line. When
CLKMD1=1, the DSP is in multiply-by-two mode. When CLKMD1=0, the DSP is in divide-by-two mode. Note that CLKMD1 may only be changed when -RS=0. Bit3 RESERVED: This bit is reserved and may reflect any value that has no relevance to the operation of
the DSP/memory module 40. Bit4 TXFULL: This bit is set to 1 when DSP writes a new data value to the DSPTXD. This bit is cleared (0) when MPU 12 completes a read from the DSPTXD. DSP should only write to DSPTXD when TXEMPTY is set (to 1) in the PCSR.
This bit is set to 0 (cleared) at power up. Bit5 RXEMPTY: This bit is set to 1 after DSP reads from DSPRXD. It is cleared when MPU 12 writes new data to DSPRXD. MPU 12 should only write to DSPRXD when RXEMPTY is 0. If MPU 12 writes to DSPRXD when
RXEMPTY is 0 previous data in DSPRXD will be overwritten. Its default value is 1. Bit6 LM_DATA_RDY: This bit is used to flag when the data register is ready to be accessed by the MPU. This bit is set to 1 by the hardware circuitry when LM_RW_DATA
register is ready to be accessed(Read or Write); it is automatically set to 0 when the LM_RW_DATA register is accessed. This bit is defined to support access to slow local memory chips, such as Flash, which may have speeds that are slower than the
MPU access speeds to the module. Default is 0. Bit7 DEVBUSYINT (Device Busy Interrupt): This bit is set to 1 after MPU 12 requests access the memory bus and does not receive access proper access. This is an error condition and thus data read is
invalid and data written is unsuccessful. This bit is reset at the beginning of every memory/DSP bus access and set to one if a timeout occurs. It should be read after a questioned access. Thus after an invalid access, the only way to clear this bit
to 0 is to get a valid access or reset the module controller. This operation is necessitated by the DSP's operation of -HOLD, - HOLDA, and READY. The default is 0. Note that the use of a long software wait state on the MPU 12 side will cause this
bit to go active. Bit8 DSP -HOLDA: This bit reflects the value of the -HOLDA (Hold Acknowledge pin) of the DSP. Bits10-9 RESERVED: These bits are reserved and may reflect any value that has no relevance to the operation of the DSP/memory module 40.
Bit11 PDH (Please Don't Hold Me): This bit is a direct copy of the PDH bit in the DSP SYSCFG register. When PDH=1, the DSP is requesting the MPU 12 not to access the memory bus. The MPU 12 may ignore the request and access the memory bus at the risk
of slowing down the DSP's code execution. Note that according to round robin bus arbitration operation, the DSP will have to finish any started bus cycles when accessing DSPSMMR's and global data memory before the MPU 12 can begin access. The only
way to guarantee MPU access is to assert -HOLD to the DSP either by MANUAL HOLD=0 or MAXOD=0. Bit15-12 RESERVED: These bits are reserved and may reflect any value that has no relevance to the operation of the DSP/memory module 40.
DSP Data Transmit Register
DSPTXD is a 16 bit register used by the DSP to communicate to the host MPU 12. The MPU 12 has only read access to this register and any MPU write to this register is ignored. The DSP has only write access to this register and any DSP read from
this register causes invalid data to be read. A DSP write to this register generates a TXFULL interrupt to the MPU 12 if enabled. Similarly, an MPU 12 read from this register generates a TXEMPTY interrupt to the DSP if enabled.
DSP Data Receive Register
DSPRXD is a 16 bit register used by the MPU 12 to communicate to the DSP. The MPU 12 has only write access to this register and any MPU 12 read from this register causes invalid data to be read. The DSP has only read access to this register and
any DSP write to this register is ignored. A DSP read from this register generates a RXEMPTY interrupt to the MPU 12 enabled. Similarly a MPU 12 write to this register generates a RXFULL interrupt to the DSP if enabled.
MPU 12 Status Register
The PCSR, shown in FIG. 4c, is a 16 bit read-only register to the DSP located at I/O address 0052h when the DSP/memory module 40 is in smart mode. It is used by the DSP space to determine status of the host communication registers. Its bits are
defined in Table VI.
TABLE VI PCSR Bit Operation Bit0 TXEMPTY: This bit is set to 1 after MPU 12 reads new data from DSPTXD. It is cleared (0) when DSP writes new data to DSPTXD indicating new data is available for MPU 12. This bit directly drives the -INT4
pin of the DSP generating a communication transmit interrupt to the DSP. The default value for this bit is 1. Bit1 RXFULL: This bit is set to 1 when MPU 12 writes new data to the DSPRXD. This bit is cleared (0) when DSP completes a read from the
DSPRXD. MPU 12 should only write new data to DSPRXD when RXEMPTY in the DSPSR is clear (0). This bit directly drives the -INT4 pin of the DSP generating a communication receive interrupt to the DSP. The default value for this bit is 0. Note that if
DSP MP/-MC bit must be equal to 1.
Bit I/O Register (Reserved)
The BIOR is a 16 bit read/write.vertline..vertline.read-only register to the DSP located at I/O address 0053 h when the DSP/memory module 40 is in Smart Mode. BIOR receives information from an analog front end (described in connection with FIG.
12) so that the DSP/memory module 40 can receive information through external signals, such as a line-in/out, microphone input, telephone line or cellular connection.
System Configuration Register
The SYSCFG register, shown in FIG. 4d, is a 16 bit read/write register to the DSP located at I/O address 0054 h when the DSP/memory module 40 is in Smart Mode. It is used by the DSP to control the frequency of the clock input to the DSP when
CLKMD1=0, bus arbitration, Global Data paging, external memory configuration and paging.
TABLE VII SYSCFG Bit Operation Bit1-0 CLKD0-CLKD1: The clock divider select bits 1-0 selects the divider for the 50 ns clock (when CLKMD1=0) as follows: CLKD1-CLKD0 VALUE DIVIDER CLKOUT1 VALUE 00 1 100 ns 01 2 200 ns 10 4 400 ns 11 8
800 ns Bit2 DSPTXDINTEN: This bit is used by the DSP to receive an interrupt when DSPTXD is read by the MPU 12. When DSPRXDINTEN is set (1), TXEMPTY condition in the PCSR will generate an interrupt to the DSP allowing interrupt driven communications
with the MPU 12. Writing a 0 will disable, but not clear the interrupt. The default value of this bit is 0. Bit3 PDH (Please Don't Hold Me): This bit is reflected as the PDH bit in the DSPSR register that requests the MPU 12 not to access the
memory bus when PDH=1. The MPU 12 may ignore the request and access the memory bus at the risk of slowing down the DSP's code execution. Note that due to DSP bus arbitration operation, the DSP will have priority to SMM registers and global data
memory. The only way to guarantee MPU 12 access is -HOLD the DSP. Bit5-4 RESERVED: 0 should always be written to these bits or unknown conditions may occur. Bit6 DSPRXDINTEN: This bit is used by the DSP to receive an interrupt when DSPRXD is written
to by the MPU 12. When DSPRXDINTEN is set (1), RXFULL condition in the PCSR will generate an interrupt to the DSP allowing interrupt driven communications with the MPU 12. Writing a 0 will disable, but not clear the interrupt. The default value of
this bit is 0. Bit7 RESERVED: 1 should always be written to this bit or unknown operation may occur. Bit11-8 RESERVED: 0 should always be written to these bits or unknown conditions may oc | | |
