A digital system in a first clock domain synchronously initializes a logic circuit having a memory characteristic. The digital system includes first and second logic circuits. The first circuit includes an asynchronous port for receiving a reset signal from a second clock domain, a port for receiving a first clock signal for the first clock domain, and an output port for providing an initialization signal. The first circuit sets the initialization signal at a first logic value in response to the reset signal and maintains the first logic value at least until the first clock signal becomes active. The second circuit includes a synchronous port for receiving the initialization signal, a port for receiving the first clock signal, and a data output port outputting a data signal. The second circuit is initialized in response to the active first clock signal when the initialization signal has the first logic value.
A reset circuit for resetting two clock domains resets the two clock domains synchronously with a first clock signal in response to assertion of a system reset. It then de-asserts the resetting of a first of the clock domains in synchronization with the first clock signal, and de-asserts the resetting of a second of the clock domains in synchronization with a second clock signal so that the second clock domain is not operative until after the second clock signal is running.
The present invention provides a storage device that enables identification data to be readily rewritten and ensures normal completion of a data writing operation in a short time period. In the storage device of the invention, an ID comparator determines whether or not identification data transmitted from a host computer coincides with identification data stored in a memory array. In the case of coincidence, the ID comparator sends an access enable signal EN to an operation code decoder. The operation code decoder analyzes a write/read command, switches over a direction of data transfer with regard to the memory array based on a result of the analysis, and requires an I/O controller to change a high impedance setting of a signal line connecting with a data terminal DT. This series of processing allows access to an address in the memory array specified by a count on an address counter.
A system and method for hardening an asynchronous combinational logic circuit against Single Event Upset (SEU) is presented. The asynchronous combinational logic circuit is located between two asynchronous registers. A fault detector is used to detect a fault at an output of the asynchronous combinational logic circuit caused by SEU. If the fault detector detects a fault, a first asynchronous register is prevented from clearing stored data and a second asynchronous register is prevented from loading data from the asynchronous combinational logic circuit until the fault is cleared. Further, a timer circuit is used to ensure enough time elapses to allow the asynchronous combinational logic circuit to reevaluate itself. The asynchronous combinational logic circuit reevaluates itself by first propagating a NULL wave front to clear the fault and then propagating the data stored in the first asynchronous register to its outputs.
