A system uses an event based equivalent time sampling method for ascertaining a value of each bit of a data frame repeated in a digital signal of indeterminate phase. The system measures time intervals between rising edges of the digital signal and a reference time and between falling edges of the digital and that reference time in response to pulses of a periodic arming signal. The measured time intervals are then normalized to equivalent time intervals and those intervals analyzed to determine values of each bit of the data frame.
The present invention relates to a method for pulse placement to form a binary pulse signal, said binary pulse signal having a constant pulse rate being reciprocal of a constant pulse rate period, comprising the steps of generating a bit clock having a bit clock period of shorter duration than said constant pulse rate period, synthesizing pulses with leading and trailing edges, said leading and trailing edges of said synthesized pulses being placed at N-multiples of said bit clock period within said constant pulse rate period, with N=0, 1, 2, . . , and selecting said bit clock period individually for successive pulses of said binary pulse signal.
Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by slowing the clock rate with respect to the sampling clock. For instance, the slower clock rate may be implemented by dividing the frequency of the sampling clock by a number such as 128, slowing a sampling clock frequency designed to handle multiple gigabits per second (Gbps) to a frequency of less than one kilohertz (Khz). In addition to the reduced power consumption realized by operating at a lower frequency, the slower clock rate allows components of the CDR loop circuitry to operate a lower operating voltage reducing power consumption by the CDR loop even more.
