An electronic camera for capturing and storing images includes an image capture section and an image processing section. The image capture section includes an image sensor for capturing an image and producing pixel data representative of the captured image, an analog-to-digital (A/D) converter for digitizing the pixel data, and a horizontal shift register responsive to applied vertical clock signals for receiving lines of the pixel data from the image sensor and responsive to applied horizontal clock signals for sequentially transferring the lines of pixel data to the A/D converter, the time between the application of horizontal and vertical clock signals providing for a vertical transfer interval wherein pixel data is prevented from being output from the horizontal shift register. The image processing section includes a first-in-first-out (FIFO) memory coupled to the A/D converter for temporarily storing the digitized pixel data, a digital signal processor coupled to the FIFO memory for processing the digitized pixel data, and a storage device coupled to the digital signal processor for storing the processed digitized pixel data. The electronic camera further includes a clock generator for producing the vertical and horizontal clock signals and a FIFO write signal for causing the digitized pixel data from the A/D converter to be transferred to storage locations in the FIFO memory at a first frequency, and a master pixel clock signal. The camera further includes circuitry for producing a FIFO read signal in response to the master pixel clock signal for transferring the digitized pixel data from the FIFO memory to the digital signal processor at a second frequency for processing the digitized pixel data, and after processing, for transferring the processed pixel data to the storage device. The second frequency is selected to be lower than the first frequency.
An imaging system controller (5) outputs a control signal (VC). The control signal (VC) gives a command to output driving clocks (.phi.Vn, .phi.Hm) of an imaging element (1) in a signal transmission period, and a command to suspend output of the clocks (.phi.Vn, .phi.Hm) in an idle period subsequent to the signal transmission period. The length of the idle period is a multiple of the length of the signal transmission period by a natural number. The imaging system controller (5) periodically repeats output of the control signal (VC) giving these commands a number of times corresponding to the number of horizontal lines of the imaging element (1). In response to the commands of the control signal (VC), a timing generator (2) generates and outputs the clocks (.phi.Vn, .phi.Hm), and suspends generation and output of the same. An imaging device (10) thereby intermittently drives the imaging element (1), to generate and output a picked-up image signal (V2).
A line buffer and a method of providing data to a 3.times.3 line interpolation processor using the line buffer in an image processing system, such as a digital camera, includes a readable and writable single memory, a buffer register having a prior data area storing first line image data, which has been stored in a memory, in a unit of 2m bits, and having a present data area storing second image data, which is inputted from an image sensor in a unit of m bits, in a unit of the 2m bits, and a memory controller providing the memory with a chip enable signal, a write enable signal, and an address indicating locations of the first and second line image data stored in the buffer register, reading and writing the first and second line image data from and on the memory, and outputting the first and second line image data and a third line image data, which is inputted from the image sensor.
A DSP system, capturing the data from a main bus via a bus operating at the clock speed of a first frequency, and sending the data to a DSP unit reading the data at the clock speed of a second frequency, the DSP system comprising: a bus control unit, which is adapted to transfer data from the main bus to the bus; a pulse wave generator, producing a pulse wave that synchronous to the bus, the pulse wave is comprised of sequential time slots, wherein a part of the time slots are DRQ slots that respectively comprises a data requesting signal, and the other times slots are normal slots; and an interface unit, capturing the data from the bus control unit via the bus according to the data requesting signal, and transmitting the data to the DSP unit. According to the DSP system of the present invention, the FIFO register that used in the prior art could be abandoned, whereby saving the occupied space of the whole system.
