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Claims  |
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What is claimed is:
1. A semiconductor circuit device, comprising:
clock generating circuitry for transmitting an internal clock signal
synchronous with an externally applied external clock signal to a
loop-shape clock transmission line having a forward path and a backward
path, said loop-shape clock transmission line being divided into said
forward path and said backward path at a returning point; and
a feedback path coupled to a middle point on the forward path of said
loop-shape clock transmission line for feeding back the internal clock
signal being transmitted over said forward path to said clock generating
circuitry, signal propagation delay of said feedback path being
substantially equal to signal propagation delay from the middle point of
said forward path to said returning point;
said clock generating circuitry including a circuit for adjusting a phase
of said internal clock signal such that the internal clock signal
transmitted through said feedback path and said external clock signal are
in phase with each other.
2. The semiconductor circuit device according to claim 1, further
comprising:
a clock input buffer receiving said external clock signal for application
to said clock generating circuitry; and
a replica buffer having a same configuration of said clock input buffer,
provided on said feedback path for receiving the internal clock signal
transmitted over said feedback path for application to said clock
generating circuitry.
3. The semiconductor circuit device according to claim 1, further
comprising:
a clock input circuit receiving said external clock signal for transmission
to said clock generating circuitry; and
a replica circuit provided on said feedback path, having substantially the
same signal transmission characteristic as said clock input circuit, for
applying a signal applied through said feedback path to said clock
generating circuitry.
4. The semiconductor circuit device according to claim 1, wherein said
returning point is a point providing a propagation delay of substantially
half a propagation delay of a whole of said loop-shape clock transmission
line.
5. The semiconductor circuit device according to claim 1, wherein said
loop-shape clock transmission line transmits a clock signal to a plurality
of internal circuits, and said returning point is provided corresponding
to one of said plurality of internal circuits, said one being physically
the farthest from said clock generating circuitry.
6. The semiconductor circuit device according to claim 1, further
comprising circuitry for generating a second internal clock signal by
combining internal clock signals on a node on the forward path and a node
on the backward path provided at mutually symmetrical positions with
respect to said returning point.
7. The semiconductor circuit device according to claim 5, further
comprising:
a plurality of first nodes provided on said forward path corresponding to
said plurality of internal circuits;
a plurality of second nodes arranged at positions symmetrical to the
respective first nodes with respect to said returning point; and
a plurality of clock reproducing circuits provided corresponding to pairs
of the first and second nodes positioned at mutually symmetrical positions
on said forward path and said backward path, for generating and applying
to corresponding internal circuits second internal clock signals each
having a central phase between internal clock signals of corresponding
first and second nodes.
8. A semiconductor circuit device, comprising:
clock generating circuitry for generating a clock signal;
a plurality of internal circuits each operating in accordance with an
applied clock signal, said plurality of internal circuits being arranged
in a region between a first node of a minimum delay physically nearest to
said clock generating circuitry and a second node of maximum delay
physically farthest from said clock generating circuitry; and
a clock distributing circuit including (i) a plurality of nodes arranged in
a form of a tree with a node corresponding to a middle point between the
first and second nodes being a starring node, each node connected to clock
transmission lines extending in mutually opposite directions and (ii)
clock drivers arranged corresponding to respective nodes for transmitting
an applied clock signals to corresponding clock transmission lines, for
transmitting the clock signal from said clock generating circuitry to said
plurality of internal circuits, wherein said clock generating circuitry
includes:
a clock buffer circuit for receiving an externally applied external clock
signal to produce a first internal clock signal according to the external
clock signal;
a phase comparator for comparing in phase the first internal clock signal
and a feedback clock signal fed back from the clock distributing circuit;
a delay stage for delaying a received clock for outputting;
a delay control circuit according to an output signal of said phase
comparator for adjusting a delay amount of said delay stage such that a
phase difference between the first internal clock signal and the feedback
clock signal becomes substantially zero;
a frequency divider for receiving a middle signal having a delay amount of
half a whole delay amount of said delay stage from said delay stage to
frequency-divide the middle signal by a predetermined factor,
a first selector responsive to a first selecting signal for selecting one
of said first internal clock signal and said middle signal for application
to said delay stage; and
a first selecting circuit responsive to an operation mode designating
signal for selecting one of an output signal of said frequency-divider and
an output of said delay stage to generate a second internal clock signal
as said clock signal.
9. The semiconductor circuit device according to claim 8, wherein said
clock generating circuitry further includes
a second selector for selecting one of said middle signal and the output
signal of the delay stage in accordance with a second selecting signal;
a third selector for selecting one of the first internal clock signal and
an output signal of said second selector for application to internal
circuitry as a timing control signal.
10. The semiconductor circuit device according to claim 8, wherein said
first selecting circuit includes
a second selector for selecting one of an output signal of said delay stage
and an output signal of said frequency-divider in accordance with a second
selecting signal included in said operation mode designating signal, and
a third selector for selecting one of an output signal of said second
selector and said first internal clock signal in accordance with a third
selecting signal included in said operation mode designating signal.
11. The semiconductor circuit device according to claim 8, further
comprising
a replica buffer for providing the feedback clock signal with a delay
substantially the same as a delay of said first internal clock signal
relative to the external clock signal.
12. The semiconductor circuit device according to claim 8, wherein said
feedback clock signal is fed back from a node physically nearest to said
clock generating circuitry among said plurality of nodes.
13. The semiconductor circuit device according to claim 8, wherein said
clock generating circuitry further comprises
a pulse generator responsive to a transition of said first internal clock
signal for generating a one-shot pulse signal, and
a phase synchronizing circuit for successively delaying said one shot pulse
signal to select a delayed one shot pulse signal locked in phase with the
one-shot pulse signal for outputting as another clock signal.
14. A semiconductor device comprising:
an internal clock generating circuitry for generating an internal clock
signal in accordance with an external clock signal;
a clock tree arranged on a common semiconductor substrate on the internal
clock generating circuitry and including a plurality of nodes for
distributing the internal clock signal from a starting point to terminal
points;
an internal control signal generator provided corresponding to a terminal
point of said plurality of terminal points and responsive to a clock
signal at the terminal point for generating an internal control signal for
controlling an internal operation;
said internal clock generating circuitry receiving a clock signal at a
predetermined terminal point of the terminal points to adjust a phase
difference between the external clock signal and the received clock signal
for generating said internal clock signal.
15. The semiconductor device according to claim 14, wherein said internal
clock signal is transmitted from a minimum delay point to a maximum delay
point, said starting point is at a middle point between said maximum delay
point and said minimum delay point, said nodes of the clock tree are
arranged in a plurality of stages, and each stage includes a branching
node for a starting node to a succeeding stage, said branching node being
located at a middle point between a corresponding starting node and the
maximum delay point.
16. The semiconductor device according to claim 14, wherein said internal
clock generating circuitry includes a clock buffer for receiving and
buffering the externally applied external clock signal, and an internal
clock generator receiving an output clock signal to generate said internal
clock signal,
said internal clock generator receives the clock signal through a replica
circuit having a common transmission characteristics as said clock buffer
to compare the received clock signal and the output clock signal received
from the clock buffer.
17. The semiconductor device according to claim 14, wherein the node of the
each stage of said clock tree is provided with a clock driver for
buffering a received clock signal.
18. The semiconductor device according to claim 14, further comprising an
internal signal latch circuit for latching an externally applied input
signal in response to said internal control signal.
19. The semiconductor device according to claim 18, wherein said internal
clock signal generating circuitry includes a feedback circuit having a
same transfer characteristics as a signal transmission delay from the
terminal point to a corresponding internal signal latch circuit, for
transferring the clock signal at the predetermined terminal point, and an
internal clock generating circuit receiving the external clock signal and
an output clock signal from the feedback circuit for adjusting a phase
difference between the external clock signal and the receiver output
signal to generate the internal clock signal.
20. A semiconductor memory device comprising:
signal input circuitry for receiving an input signal and generating an
internal signal;
latch circuitry for receiving and latching said internal signal; and
control signal generating circuitry for generating an input control signal
controlling taking in of said input signal by said input circuitry and a
latch control signal controlling latching operation of said latch
circuitry in accordance with a basic signal, said control signal
generating circuitry including an adjusting circuit for compensating for a
time difference between taking in of said input signal by said input
circuitry and latching of said internal signal by said latch circuitry,
wherein said adjusting circuit comprises delay circuitry for delaying said
input control signal, by a time period corresponding to a signal
propagation time of said internal signal from said input circuitry to said
latch circuitry, to generate said latch control signal.
21. A semiconductor memory device comprising:
signal input circuitry for receiving an input signal and generating an
internal signal;
latch circuitry for receiving and latching said internal signal; and
control signal generating circuitry for generating an input control signal
controlling taking in of said input signal by said input circuitry and a
latch control signal controlling latching operation of said latch
circuitry in accordance with a basic signal, said control signal
generating circuitry including an adjusting circuit for compensating for a
time difference between taking in of said input signal by said input
circuitry and latching of said internal signal by said latch circuitry,
wherein said adjusting circuitry comprises a delay circuit for adjusting a
phase difference between said input control signal and said latch control
signal.
22. A semiconductor device comprising:
adjusting circuitry for adjusting a phase difference between an external
clock signal applied to an external clock input node and a feed back
internal clock signal at a feed back clock node fed back from a
predetermined internal clock mode receiving an internal clock signal, and
generating a reference internal clock signal and a pro-external clock
signal; and
internal clock generating circuitry for generating said internal clock
signal synchronized with said external clock signal in accordance with
said reference clock signal and said pro-external clock signal;
said adjusting circuitry adjusting said phase difference such that a
propagation delay of the external clock signal between the external clock
input node and an input of said internal clock generating circuitry is
made equal to a propagation delay of the feed back clock signal between
the predetermined internal clock node and the input of the internal clock
generating circuitry.
23. The semiconductor device according to claim 22, wherein said adjusting
circuitry comprises:
an external clock buffer circuit for buffering said external clock signal
applied to said external clock input node to generate said pro-external
clock signal, and
an internal clock buffer circuit being the same in configuration and size
with said external clock buffer and arranged between said feed back clock
signal input node and an input of said internal clock signal generating
circuitry, for buffering said feed back internal clock signal.
24. The semiconductor device according to claim 23, further comprising a
delay circuit formed of an interconnection line patterned into a
predetermined layout form and connected between said internal clock buffer
circuit and said input of said internal clock signal generating circuitry.
25. The semiconductor device according to claim 23, wherein said internal
clock generating circuitry comprises, at said input, a phase comparison
circuit for comparing phases of received clock signals.
26. The semiconductor device according to claim 22, wherein
said predetermined internal clock node is a node on an internal clock
signal transmitting line transmitting said internal clock signal from said
internal clock signal generating circuitry to internal circuitry, and
said internal clock is fed back through a feed back line connected between
said predetermined internal clock node and said feed back clock node and
arranged separately from said internal clock signal transmitting line.
27. The semiconductor device according to claim 26, wherein said
predetermined internal clock node is a node at a mid-point between a
physically farthest point from said internal clock signal generating
circuitry of said internal clock transmitting line and said internal clock
signal generating circuitry. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor circuit device and, more
specifically, to a configuration for distributing an internal clock signal
in a circuit device operating in synchronization with the clock signal.
More specifically, the present invention relates to a configuration for
distributing an internal clock signal in a clock synchronous semiconductor
memory device in which taking of an external signal and data and output of
data are performed in synchronization with an externally applied clock
signal.
2. Description of the Background Art
FIG. 32 schematically represents an overall configuration of a convention
al clock synchronous semiconductor memory device. Referring to FIG. 32,
the clock synchronous semiconductor memory device includes a memory array
900 having a plurality of memory cells arranged in a matrix of rows and
columns; a synchronizing circuit 902 receiving an externally applied clock
signal EXCLK and generating an internal clock signal INCLK synchronized
with the external clock signal EXCLK; an address input circuit 904 taking
in an externally applied address signal AD in synchronization with the
internal clock signal INCLK from synchronizing circuit 902 and generating
an internal address signal; a control signal input circuit 906 taking an
external command .PHI.C in synchronization with the internal clock signal
INCLK and generating an internal control signal; a control circuit 908
generating various control signals necessary for a designated operation
mode in accordance with the internal control signal from control signal
input circuit 906; a cell selecting circuit 910 operating under the
control of control circuit 908, and selecting a memory cell in memory cell
array 900 in accordance with the internal address signal applied from
address input circuit 904; and a data input/output circuit 912 operating
under the control of control circuit 908 and performing data input/output
to and from the memory cell selected by cell selecting circuit 910 in
synchronization with internal clock signal INCLK.
The command signal .phi.C includes a plurality of external control signals
such as a row address strobe signal ZRAS, a column address strobe signal
and a write enable signal ZWE, and by a combination of states of the
plurality of external control signals at a rising edge of the internal
clock signal INCLK, a command designating an operation mode is formed.
FIG. 33 is a timing chart representing an operation of the clock
synchronous semiconductor memory device shown in FIG. 32. In the
following, the operation of the clock synchronous semiconductor memory
device shown in FIG. 32 will be described with reference to FIG. 33.
In a cycle preceding a cycle #a of external clock signal EXCLK, an active
command is applied and in memory array 900, memory cells corresponding to
an addressed row are driven to and held at a selected state.
In the clock cycle #a, the command signal .phi.C is set to a prescribed
state, and a write command designating a data write is applied. In the
clock cycle #a, in synchronization with a rise of external clock signal
EXCLK, address input circuit 904 takes in the external address signal AD
and generates an internal address signal. Data input/output circuit 912
takes in externally applied write data d0 in synchronization with the
external clock signal EXCLK in accordance with the write command. Cell
selecting circuit 910 selects a memory cell in accordance with the address
signal applied from address input circuit 904.
In successive clock cycles starting at clock cycle #a, write data d1, d2
and d3 are taken in, respectively in synchronization with the rise of the
external clock signal EXCLK. The write data d0 to d3 are written to memory
cells selected by the cell selecting circuit 910 of memory array 900 in a
prescribed sequence. The number of data written or read successively when
a command is applied is referred to as a burst length. FIG. 33 represents
an example of a data writing operation when the burst length is 4.
In a cycle #b of external clock signal EXCLK, the command signal .phi.C is
set to a prescribed state and a read command designating a data read is
applied. In accordance with the read command, address input circuit 904
takes in an external address signal AD in synchronization with a rise of
external clock signal EXCLK and generates an internal address signal. Cell
selecting circuit 910 selects an addressed memory cell of memory array
900, and data of the selected memory cell is applied to data input/output
circuit 912. A certain time period is necessary from the selection of the
memory cell by cell selecting circuit 910 until transfer of data of the
selected memory cell to data input/output 912. In a cycle preceding the
cycle #c of external clock signal EXCLK, valid data is output from data
input/output circuit 912, the read data q0 is established at a rising edge
of external clock signal EXCLK in the clock cycle #c and sampled by an
external device. Thereafter, data of the burst length are read in
synchronization with the external clock signal EXCLK successively. The
clock cycle period from clock cycle #b to clock cycle #c is generally
referred to as CAS latency, and FIG. 33 represents an example of a reading
operation where CAS latency is 3.
In a clock synchronous semiconductor memory device such as the one shown in
FIG. 32, the external address signal and the command signal are taken in
synchronization with external clock signal EXCLK (internal clock signal
INCLK). Therefore, it is unnecessary to consider any skew between control
signals, and a timing of starting an operation of the internal circuit can
be made advanced, enabling high speed access.
Further, since data input/output is also in synchronization with the
external clock signal EXCLK, data transfer rate is effectively the same as
the rate of the external clock signal EXCLK, and therefore high speed data
transfer is realized.
Synchronizing circuit 902 generates the internal clock signal INCLK which
is synchronous with the externally applied clock signal EXCLK, and
determines the timing of taking signals of address input circuit 904 and
control signal input circuit 906. Therefore, in address input circuit 904
and control signal input circuit 906, taking of accurate external signals
and generation of internal signals at a faster timing are possible.
Further, in data input/output circuit 912, it is possible to input/output
data in accordance with the external clock signal EXCLK, and therefore
accurate data input/output and high speed data transfer can be realized.
FIG. 34A represents a schematic configuration of the synchronizing circuit
shown in FIG. 32. Synchronizing circuit 902 shown in FIG. 34A is formed by
a synchronizing circuit having a feed back loop such as a phase locked
loop (PLL). Synchronizing circuit 902 adjusts phase of the internal clock
signal INCLK such that the externally applied external clock signal EXCLK
and the internal clock signal INCLK come to have the same phase.
Therefore, as can be seen from FIG. 34B, the internal clock signal INCLK
is in phase with the external clock signal EXCLK.
The external control signal and the address signal are generated with the
external clock signal EXCLK being a reference. Therefore, in the
semiconductor memory device, the command signal .phi.C has extremely small
skew with respect to the external clock signal EXCLK (with the direction
of signal transfer being the same), and therefore sufficient set up time
Ts and sufficient hold time Th are ensured. It should be noted, however,
that though synchronizing circuit 902 has a function of making the phase
of internal clock signal INCLK matched with external clock signal EXCLK,
synchronizing circuit 902 does not have a function of adjusting skew
generated n the internal clock signal INCLK is transmitted inside the
semiconductor memory device.
FIG. 35A schematically shows a manner of distribution of the internal clock
signal from synchronizing circuit 902. In FIG. 35A, the internal clock
signal from synchronizing circuit 902 is transmitted to input circuits
#ai, #bi and #ci through respective clock transmission lines (signal
lines) L1, L2 and L3. The clock transmission lines L1, L2 and L3 have
different line capacitances and different line resistances, and hence
different signal propagation delays. In FIG. 35A, internal clocks INCLKa,
INCLKb and INCLKc are shown respectively to be transmitted to clock
transmission lines L1, L2 and L3 from synchronizing circuit 902. Clock
transmission lines L1, L2 and L3 have larger signal propagation delays in
this order. Input circuit #ai to #ci may be any of input circuits 904, 906
and 912 shown in FIG. 32.
FIG. 35B schematically represents timing relation between the clock signals
shown in FIG. 35A and a signal SIG applied to the input circuit. In FIG.
35B, in a cycle #ca of the external clock signal EXCLK, the signal SIG is
applied. At this time, when time difference between internal clock signal
INCLKa, INCLKb and INCLKc is small and the clock skew is small, it is
possible to take the signal SIG into respective input circuits #ai to #ci
at a rising edge of external clock signal EXCLK to generate internal
signals. The signal SIG represents a group of signals applied to input
circuit #ai to #ci, respectively. In this case, however, it is necessary
to determine the timing of starting an internal operation, taking into
consideration the clock skew, and therefore the timing of starting an
internal operation is delayed. If the hold time of the signal SIG is
insufficient, it becomes impossible to generate a correct internal signal.
When the external clock signal EXCLK is a high speed clock signal (having
high frequency) as represented by the cycle #cb of the external clock
signal EXCLK in FIG. 35B, time difference between signal clock signals
INCLKa to INCLKc is relatively large, and when the clock skew is large,
the signal SIG which is to be taken in at a rising edge of the external
clock signal EXCLK cannot be taken with the internal clock signal INCLKc
applied to input circuit #ci. Therefore, when the clock skew is large, it
is impossible to execute the designated operation. Accordingly, the
operation frequency of the semiconductor memory device is determined by
the clock skew, which means that high speed operation is not possible.
More specifically, when the clock skew occupies a major part of the cycle
time of the external clock signal, accurate operation becomes impossible,
and hence the operation frequency of the semiconductor memory device is
significantly limited by the clock skew.
FIG. 36A schematically represents a configuration of a data output portion
of data input/output circuit 912 of FIG. 32. Referring to FIG. 36A, there
are a plurality of data output circuits OB#0 to OB#n provided parallel to
each other. To these data output circuits OB#0 to OB#n, internal clock
signal INCLK is transmitted through a clock transmission line L4 from
synchronizing circuit 902. Data output circuits OB#0 to OB#n transfer and
output data in synchronization with an internal clock signal INC (INC0 to
INCn) applied through clock transmission line L4. There is also a clock
skew derived from difference in line length in clock transmission line L4.
FIG. 36B is a timing chart representing an operation of the data output
portion of FIG. 36A. Data output circuit OB#0 is nearest to synchronizing
circuit 902, clock transmission line L4 thereto is the shortest, and the
delay of internal clock signal INC0 with respect to external clock signal
EXCLK is the smallest. Data output circuit OB#n is farthest from
synchronizing circuit 902, clock transmission line L4 thereto is the
longest, and propagation delay is the largest.
Data output circuits OB#0 to OB#n transfer and output data in
synchronization with the applied internal clock signals INC0 to INCn at
the time of a data read. Therefore, data Q0 output from data output
circuit OB#0 attains to the established state at the earliest timing,
while data Qn output from data output circuit OB#n attains to the
established state at the latest timing.
Accordingly, data output timings of data output circuits OB#0 to OB#n delay
because of the delays in internal clock signals INC0 to INCn, and
therefore set up times of data Q0 to Qn with respect to the external clock
sign al EXCLK become shorter by the delay times of the internal clock
signals, and hence output data come to have smaller margins (as the
external device samples data at the rising edge of external clock signal
EXCLK).
As represented by the dotted line for the data Qn in FIG. 36B, when the
clock skew becomes so large that the timing of establishment of data Qn
becomes later than the rising edge of the external clock signal EXCLK,
accurate data reading is impossible. Therefore, in the data output
operation also, operation frequency of data output is determined by the
clock skew over the clock transmission line L4, that is, delay time
difference among internal clock signals INC0 to INCn. Especially in recent
semiconductor memory devices, multiple bits of data such as 16 bits are
output, which means that there are larger number of data output circuits
OB#0 to OB#n, and hence clock skew over clock transmission line L4 tends
to be larger, resulting in the problem that accurate data output in
synchronization with the high speed clock signal becomes difficult.
FIG. 37 represents another configuration of a conventional semiconductor
memory device. Referring to FIG. 37, in synchronization with the internal
clock signal INCLK from synchronizing circuit 920, internal circuits NK#0
to NK#n operate. It is not necessary for these internal circuits NK#0 to
NK#n to execute the same processing contents. What is necessary is that in
the configuration, prescribed processings are performed, with the
operation cycle defined by the internal clock signal INCLK applied through
clock transmission line LK. In other words, the semiconductor circuit
device may be a general arithmetic processing device.
In such a semiconductor circuit device as shown in FIG. 37 also, the
internal clock signal INCLK is transmitted from synchronizing circuit 920
over clock transmission line LK to internal circuits NK#0 to NK#n. Among
internal circuits NK#0 to NK#n, the are exists one internal circuit which
receives the internal clock signal with minimum delay amount, and one
internal circuit which receives the internal clock signal with maximum
delay amount. Therefore, in this case also, it is necessary to operate
internal circuits NK#0 to NK#n, taking into account the skew of internal
clock signal INCLK transmitted over clock transmission line L5, and
therefore there is the problem that high speed operation is not possible.
Especially when the semiconductor circuit device is implemented in large
scale and the number of circuits connected to clock transmission lines L1
to L5 increases, the load on the clock transmission lines increases
accordingly, signal propagation delay over the clock transmission lines
increases, and the problem of clock skew becomes more serious. In order to
solve the problem of clock skew experienced in the semiconductor circuit
devices such as shown in FIGS. 35A, 36A and 37, a configuration have been
proposed in which dummy delays for adjusting delay times are arranged in
accordance with the amounts of respective clock delays.
FIG. 38 represents an example of a counter measure against clock skew in
the conventional semiconductor circuit device. In FIG. 38, internal
circuitry is divided into a plurality of internal circuit groups NG#0 to
NG#m. For internal circuit groups NG#0 to NG#(m-1), dummy delays DDL#0 to
DDL#(m-1) for adjusting delay time are arranged. The internal clock signal
INCLK from synchronizing circuit 925 is transmitted over a clock
transmission line L6, the internal clock signal is transmitted to internal
circuit groups NG#0 to NG#(m-1) through corresponding dummy delays DDL#0
to DDL#(m-1), respectively, and to internal circuit group NG#m, internal
clock signal INCLK from clock transmission line L6 is transmitted.
Each of dummy delays DDL#0 to DDL#(m-1) is constituted by an RC delay
circuit having a resistor and a capacitor, or a delay circuit employing an
inverter, and adapted to have such a delay amount that compensates for the
delay time over clock transmission line L6. More specifically, the delay
timed of dummy delay DDL#0 provided corresponding to internal circuit
group NG#0 provided at a point of minimum delay has approximately the same
magnitude as the clock delay derived from a load accompanying the overall
clock delay line L6. By contrast, the amount of delay of dummy delay
DDL#(m-1) is set to compensate for the delay experienced by the internal
circuit group NG#m, which is the maximum amount of delay.
In each of the internal circuit groups NG#0 to NG#m, there are a plurality
of internal circuits to which an internal clock signal is applied in
common.
In the configuration shown in FIG. 38, it is necessary to provide dummy
delays DDL#0 to DDL#(m-1) for internal circuit group NG#0 to NG#(m-1).
Accordingly, larger area is occupied by the circuit portion for
transmitting the clock signal, which hinders higher degree of integration.
Though dummy delays DDL#0 to DDL#(m-1) are set to have such delay times
that compensate for the delay time on the later stage (down stream) side
of clock transmission line L6, it is difficult to set an accurate delay
time, and it is difficult to provide internal clock signals of the same
phase accurately to internal circuit groups NG#0 to NG#m. Further, in each
of internal circuit groups NG#0 to NG#m, the applied internal clock signal
is distributed to internal circuits contained therein. Here, propagation
delay of the clock to each of the internal circuits is not constant, and
therefore in each of the internal circuit groups NG#0 to NG#m, there
exists clock skew among the internal circuits contained therein.
Further, the problem of lower operation frequency resulting from the skew
in internal clock signal described above is experienced not only in the
semiconductor integrated circuit device integrated on a single
semiconductor chip but also in a configuration in which a plurality of
integrated circuit devices are arranged on a board, as the timing of
operation of each semiconductor integrated circuit device is offset
because of the signal propagation delay over the lines on the board.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor circuit
device free from any internal clock signal skew.
Another object of the present invention is to provide a semiconductor
circuit device provided with a clock distributing circuit allowing
application of internal clock signals in phase with each other to various
internal circuits.
The semiconductor circuit device in accordance with a first aspect includes
a clock generating circuit for generating a clock signal, and a plurality
of internal circuits operating in accordance with received clock signals.
The plurality of internal circuits are arranged between a first node of a
minimum delay physically nearest to the clock generating circuit, and a
second node of a maximum delay physically the farthest from the clock
generating circuit.
The semiconductor circuit device in accordance with the first aspect
further includes a clock distributing circuit having a plurality of nodes
arranged in a shape of a tree with a node corresponding to a middle point
between the first and second nodes being a starting node, and connected to
clock transmission lines extending in opposite directions, and clock
drivers arranged corresponding to respective nodes for transmitting the
clock signals applied to the corresponding nodes to the corresponding
clock transmission lines. The clock distributing circuit transmits the
clock signal from the clock generating circuit to the plurality of
internal circuits.
The semiconductor circuit device in accordance with a second aspect
includes a clock generating circuit for generating a clock signal, and a
clock distributing circuit for distributing the clock signal of the clock
generating circuit from a nearest point physically nearest to the clock
generating circuit to a region providing a farthest point physically the
farthest therefrom. The distributing circuit has a plurality of nodes
arranged in the shape of a tree, with a middle point between the nearest
and the farthest points as a starting node. To each node, a driver for
transmitting the applied signal and signal transmission lines extending in
directions opposite to each other, having substantially the same delay and
receiving the signal from the driver, are connected. The delay of the
signal transmission line is monotonously decreased nearer to the distal
end of the tree.
The semiconductor circuit device in accordance with a third aspect includes
clock generating cir | | |
