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Claims  |
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What is claimed is:
1. A memory system comprising: a signaling path; a memory controller coupled to the signaling path; a clock generator to generate a first clock signal; and a memory device
coupled to the signaling path and to the clock generator, the memory device including timing circuitry to generate a second clock signal having a first phase offset, relative to the first clock signal, that is determined at least in part by a signal
propagation time on the signaling path, wherein the memory device further includes receive circuitry to receive information from the memory controller via the signaling path under timing control of the second clock signal.
2. The memory system of claim 1 wherein the first phase offset represents a combination of phase offset components including a first component to delay the phase of the second clock signal relative to the first clock signal according to the
signal propagation time.
3. The memory system of claim 2 wherein the combination of phase offset components further includes a second component to delay the phase of the second clock signal relative to the first clock signal according to a phase difference between the
first clock signal and a third clock signal that is used to time transmission of the information by the memory controller.
4. The memory system of claim 3 further comprising a clockline coupled to the clock generator, the memory controller and the memory device, and wherein the first clock signal is a version of an original clock signal output on the clockline by
the clock generator after the original clock signal has propagated on the clockline from the clock generator to the memory device and wherein the third clock signal is a version of the original clock signal after the original clock signal has propagated
on the clockline from the clock generator to the memory controller.
5. The memory system of claim 3 further comprising: a first integrated circuit that includes the memory controller and the clock generator; a second integrated circuit that includes the memory device; and a clockline coupled between the memory
controller and the memory device, wherein the third clock signal is generated by the clock generator and the first clock signal is a version of the third clock signal after the third clock signal has propagated on the clockline from the memory controller
to the memory device.
6. The memory system of claim 5 further comprising a crystal oscillator to output a frequency reference signal to the clock generator, the clock generator generating the third clock signal based on the frequency reference signal.
7. The memory system of claim 2 wherein the timing circuitry within the memory device further generates a third clock signal having a second phase offset, the second phase offset representing a combination of phase offset components that
includes a phase offset component to advance the phase of the third clock signal relative to the first clock signal according to the signal propagation time.
8. The memory system of claim 7 wherein the memory device further includes transmit circuitry to transmit information to the memory controller via the signaling path under timing control of the third clock signal.
9. The memory system of claim 2 wherein the combination of phase offset components further includes a second component to advance the phase of the second clock signal relative to the first clock signal according to a setup time of the receive
circuitry.
10. The memory system of claim 1 wherein the memory device further includes transmit circuitry to transmit information to the memory controller via the signaling path under timing control of the second clock signal.
11. The memory system of claim 1 wherein the timing circuitry includes a first phase offset register that is programmable to set the first phase offset.
12. The memory system of claim 1 wherein the memory controller and the memory device include calibration control circuitry to communicate a predetermined sequence of bits over the signaling path in a calibration operation to determine the first
phase offset.
13. The memory system of claim 1 wherein the memory controller and the memory device each include calibration control circuitry to determine a range of phase offset values over which a test sequence of bits is accurately communicated between the
memory device and the memory controller via the signaling path, the first phase offset being selected from within the range of phase offset values.
14. The memory system of claim 13 wherein the first phase offset falls midway between upper and lower bounds of the range of phase offset values.
15. A memory system comprising: a signaling path; a memory controller coupled to the signaling path; a clock generator to generate a first clock signal; and a memory device coupled to the signaling path and to the clock generator, the memory
device including timing circuitry to generate a second clock signal having a first phase offset, relative to the first clock signal, that is determined at least in part by a signal propagations time on the signaling path, wherein the first phase offset
represents a combination of phase offset components including a first component to advance the phase of the second clock signal relative to the first clock signal according to the signal propagation time, wherein the memory device further includes
transmit circuitry to transmit information to the memory controller via the signaling path under timing control of the second clock signal.
16. The memory system of claim 15 wherein the combination of phase offset components further includes a second component to adjust the phase of the second clock signal relative to the first clock signal according to a phase difference between
the first clock signal and a third clock signal that is used to time receipt of the information by the memory controller.
17. The memory system of claim 15 wherein the combination of phase offset components further includes a second component to advance the phase of the second clock signal relative to the first clock signal according to an output delay of the
transmit circuitry.
18. A memory system comprising: a signaling path; a memory controller coupled to the signaling path; a clock generator to generate a first clock signal; and a memory device coupled to the signal path and to the clock generator, the memory
device including timing circuitry to generate transmit and receive clock signals having respective phase offsets from the first clock signal according to respective transmit and receive phase offset values within the memory device.
19. The memory system of claim 18 further comprising transmit circuitry to transmit information on the signaling path under timing control of the transmit clock signal and receive circuitry to receive information on the signaling path under
timing control of the receive clock signal.
20. The memory system of claim 18 wherein the timing circuitry includes a transmit phase offset register to store the transmit phase offset value and a receive phase offset register to store the receive phase offset value.
21. The memory system of claim 20 wherein the memory controller and the memory device each include timing calibration circuitry to communicate at least one predetermined sequence of bits over the signaling path in a calibration operation to
determine the transmit phase offset value and the receive phase offset value.
22. The memory system of claim 21 wherein the timing calibration circuitry within the memory device is configured to update the transmit and phase offset values within the transmit and receive phase offset registers, respectively, during the
calibration operation.
23. The memory system of claim 18 wherein the transmit phase offset value represents a combination of phase offset components comprising: a first phase component to advance the phase of the transmit clock signal relative to the first clock
signal according to a propagation time of a signal communicated between the memory controller and the memory device on the signaling path; and a second phase component to delay the phase of the transmit clock signal relative to the first clock signal
according to a phase difference between the first clock signal and a second clock signal that is used to time reception of information on the signaling path by the memory controller.
24. The memory system of claim 23 wherein the receive phase offset value represents a combination of phase offset components comprising: a third phase component to delay the phase of the receive clock signal relative to the first clock signal
according to the propagation time; and a fourth phase component to delay the phase of the receive clock signal relative to the first clock signal according to the phase difference between the first clock signal and the second clock signal.
25. The memory system of claim 18 wherein the first clock signal has a lower frequency than the transmit and receive clock signals.
26. A semiconductor memory device comprising: a clock input to receive a first external clock signal; and timing circuitry including a receive phase offset register and a transmit phase offset register, the timing circuitry being coupled to the
clock input to generate receive and transmit clock signals having respective phase offsets from the first external clock signal according to respective phase offset values within the receive and transmit phase offset registers.
27. The memory device of claim 26 further comprising: a bus interface; transmit circuitry coupled to the timing circuitry to receive the transmit clock signal therefrom and to the bus interface, the transmit circuitry being configured to
transmit information via the bus interface under timing control of the transmit clock signal; and receive circuitry coupled to the timing circuitry to receive the receive clock signal therefrom and to the bus interface, the receive circuitry being
configured to receive information via the bus interface under timing control of the receive clock signal.
28. The memory device of claim 26 wherein the timing circuitry further includes transmit and receive locked-loop circuits to generate the transmit and receive clock signals, respectively, each of the transmit and receive locked-loop circuits
having a reference input coupled to the clock input and a phase offset circuit, the phase offset circuit within the transmit locked-loop circuit being coupled to the transmit phase offset register to adjust the phase of the transmit clock signal
according to the phase offset value therein, and the phase offset circuit within the receive locked-loop circuit being coupled to the receive phase offset register to adjust the phase of the receive clock signal according to the phase offset value
therein.
29. The memory device of claim 28 wherein each of the transmit and receive locked-loop circuits is a delay-locked-loop circuit.
30. The memory device of claim 28 wherein each of the transmit and receive locked-loop circuits is a phase-locked-loop circuit.
31. The memory device of claim 30 wherein each of the transmit and receive phase-locked-loop circuits multiplies the frequency of the first external clock signal such that the receive and transmit clock signals each have a higher frequency than
the first external clock signal.
32. The memory device of claim 30 wherein each of the transmit and receive phase-locked-loop circuits multiplies the frequency of the first external clock signal by a ratio M/N, M and N each being integers.
33. The memory device of claim 26 further comprising calibration control circuitry to update the phase offset values within the receive and transmit phase offset registers according to calibration commands received from a memory controller.
34. The memory device of claim 33 further comprising an signaling interface to receive the calibration commands from the memory controller.
35. A memory controller comprising: a signaling interface to communicate with a memory device; and calibration control circuitry to communicate with the memory device via the signaling interface in a calibration operation to determine transmit
and receive phase offset values that are applied to timing circuitry within the memory device to generate respective transmit and receive clock signals, the transmit phase offset value representing a phase offset between the transmit clock signal and a
second clock signal supplied to a clock input of the memory device, and the receive phase offset value representing a phase offset between the receive clock signal and the second clock signal.
36. The memory controller of claim 35 wherein the calibration control circuitry includes circuitry to receive a respective sequence of bits from the memory device for each of a plurality of phase offsets of the transmit clock signal to identify
a range of phase offsets within the plurality of phase offsets over which the corresponding received sequences of bits match a test sequence of bits, the transmit phase offset value being selected from within the range of phase offsets.
37. The memory controller of claim 35 wherein the calibration control circuitry includes circuitry to transmit a respective sequence of bits from the memory device for each of a plurality of phase offsets of the receive clock signal to identify
a range of phase offsets within the plurality of phase offsets over which the corresponding transmitted sequences of bits, after being received in the memory device, match a test sequence of bits, the receive phase offset value being selected from within
the range of phase offsets.
38. A method of communicating information between a memory controller and a memory device, the method comprising: generating a first clock signal within the memory device, the first clock signal having a phase offset relative to a second clock
signal that is determined at least in part by a signal propagation time on a signaling path between the memory device and the memory controller; timing communication of information between the memory device and the memory controller on the signaling
path using the first clock signal, wherein timing communication of information between the memory device and the memory controller comprises transmitting information from the memory device to the memory controller under timing control of the first clock
signal; generating a third clock signal within the memory device, the third clock signal having a phase offset relative to the second clock signal that is determined at least in part by the signal propagation time; and receiving information from the
memory controller within the memory device under timing control of the third clock signal.
39. The method of claim 38 wherein generating a third clock signal comprises generating a third clock signal that leads the first clock signal by a phase offset that is determined at least in part by the signal propagation time.
40. A method of communicating information between a memory controller and a memory device, the method comprising: generating a first clock signal within the memory device, the first clock signal having a phase offset relative to a second clock
signal that is determined at least in part by a signal propagation time on a signaling path between the memory device and the memory controller; and timing communication of information between the memory device and the memory controller on the signaling
path using the first clock signal, wherein generating a first clock signal having a phase offset relative to a second clock signal comprises offsetting the phase of the first clock signal relative to the second clock signal according to value stored in a
phase offset register within the memory device.
41. A method of communicating information between a memory controller and a memory device, the method comprising: generating a first clock signal within the memory device, the first clock signal having a phase offset relative to a second clock
signal that is determined at least in part by a signal propagation time on a signaling path between the memory device and the memory controller; and timing communication of information between the memory device and the memory controller on the signaling
path using the first clock signal, wherein timing communication of information between the memory device and the memory controller comprises receiving information from the memory controller within the memory device under timing control of the first clock
signal.
42. A method of communicating information between a memory controller and a memory device, the method comprising: generating, within the memory device, transmit and receive clock signals that have respective phase offsets from a reference clock
signal according to values stored in respective transmit and receive phase offset registers within the memory device; transmitting information from the memory device to the memory controller in response to transitions of the transmit clock signal; and
receiving information from the memory controller in the memory device in response to transitions of the receive clock signal.
43. The method of claim 42 further comprising communicating at least one predetermined sequence of bits between the memory controller and the memory device in a calibration operation to set the respective values in the transmit and receive phase
offset registers.
44. The method of claim 42 wherein generating the transmit and receive clock signals comprises generating transmit and receive clocks that have a higher frequency than the reference clock signal.
45. A method of operation within a semiconductor memory device, the method comprising: generating transmit and receive clock signals that have respective phase offsets from a reference clock signal according to values stored in respective
transmit and receive phase offset registers within the memory device; transmitting information via an external signal path in response to transitions of the transmit clock signal; and receiving information via the external signal path in response to
transitions of the receive clock signal.
46. The method of claim 45 further comprising transmitting a predetermined sequence of bits to a memory controller via the external signal path in a calibration operation to set the value stored in the transmit phase offset register.
47. The method of claim 45 further comprising receiving a predetermined sequence of bits from a memory controller via the external signal path in a calibration operation to set the value stored in the receive phase offset register.
48. The method of claim 45 wherein generating the transmit and receive clock signals comprises generating transmit and receive clocks that have a higher frequency than the reference clock signal.
49. A method of controlling a semiconductor memory device within a memory system, the method comprising: communicating with the memory device in a calibration operation to determine a transmit phase offset value that is applied to timing
circuitry within the memory device to generate a transmit clock signal, the transmit phase offset value representing a phase offset between the transmit clock signal and a second clock signal supplied to a clock input of the memory device; and
communicating with the memory device in a calibration operation to determine a receive phase offset value that is applied to timing circuitry within the memory device to generate a receive clock signal, the receive phase offset value representing a phase
offset between the receive clock signal and the second clock signal.
50. The method of claim 49 wherein communicating with the memory device in a calibration operation to determine a transmit phase offset value comprises: receiving a respective sequence of bits from the memory device for each of a plurality of
phase offsets of the transmit clock signal to identify a range of phase offsets within the plurality of phase offsets over which the corresponding received sequences of bits match a test sequence of bits; and selecting the transmit phase offset value
from within the range of phase offsets.
51. The method of claim 49 wherein communicating with the memory device in a calibration operation to determine a receive phase offset value comprises: transmitting a respective sequence of bits to the memory device for each of a plurality of
phase offsets of the receive clock signal to identify a range of phase offsets within the plurality of phase offsets over which the corresponding transmitted sequences of bits, after being received in the memory device, match a test sequence of bits;
and selecting the receive phase offset value from within the range of phase offsets. |
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Description |
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FIELD OF THE INVENTION
The present invention relates to communication systems, and more particularly to apparatus and methods for high speed signaling.
ART BACKGROUND
In systems which require high speed transmission of data between two or more integrated circuit devices, it is common for a timing signal to be transmitted in parallel with the data signal. By this arrangement, sometimes referred to as "source
synchronous timing," the timing and data signals experience similar propagation delays, providing the receiving device with a timing reference having a controlled phase relationship with the data signal. Circuitry within the receiving device samples the
incoming data signal at a time determined by the timing signal and its phase relationship with the data signal.
FIGS. 1A and 1B illustrate prior-art memory systems that use variants of source-synchronous timing. In the system of FIG. 1A, a folded clockline 12 is used to carry a clock signal toward a controller 10 on a first segment of the clockline and
away from the controller on a second segment of the clockline. The clock signal is generated by a clock generator 18. Each of the memory devices 14 includes a pair of clock inputs coupled respectively to the two segments of the folded clockline. The
memory devices transmit information to the controller on a data/control path 16 in a fixed phase relationship with the clock signal as it propagates toward the controller on the first clockline segment, and receive information from the controller via the
data/control path according to a fixed phase relationship between the information and the clock signal propagating away from the controller on the second clockline segment. Typically, the controller is coupled to the clockline at the fold so that the
timing references that it uses for transmit and receive are in phase. By providing source synchronous timing references in this way, timing skew problems that plague other types of high-speed signaling systems are avoided.
In the memory system of FIG. 1B, the memory devices 20 are coupled to a memory controller 21 via respective data paths 23 and also via respective pairs of strobe paths 24. A clock generator 22 is used to provide a frequency reference to the
memory controller and each of the memory devices. In operation, the memory controller asserts a strobe signal on one of the pair strobe paths to provide a timing reference for transmission of data to a memory device, and a memory device asserts a strobe
signal on the other of the pair of strobe paths to provide a timing reference for transmission of data to the controller. Typically, strobe signal paths are routed and conditioned to equalize the propagation times between strobe signals and
corresponding data transmissions. Consequently, the strobe signals constitute source synchronous timing references that facilitate high-speed signaling without timing skew.
One disadvantage of the prior art systems of FIGS. 1A and 1B is that additional pins are required on the memory controller and slave devices, and additional traces are required on the circuit board to support transmission of the source
synchronous timing references. The proliferation of traces is particularly problematic in the system of FIG. 1B, because the number of strobe paths is a multiple of the number of memory devices. Consequently, the routing of timing and data paths in
such systems is often complex, involving a dozen or more circuit board layers.
Another disadvantage of the prior art systems of FIGS. 1A and 1B is the additional layout complexity that results from the need to equalize the electrical lengths of the timing and data paths to avoid skew between the timing and data signals.
Electrical length equalization is particularly challenging in view of the fact that the data path is typically a multi-conductor path having a higher parasitic capacitance than the timing reference paths. Again, the large number of strobe paths required
in the system of FIG. 1B further complicates matters. Numerous passive devices are often used for electrical length equalization in such systems, necessitating additional printed circuit board layers.
SUMMARY OF THE INVENTION
A single-clock, strobeless signaling system is disclosed. In one embodiment, the signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The
slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied by the clock generator, the phase offset being determined at least in part by a signal propagation time on the signal
path. Various alternative embodiments of the signaling system are disclosed as are embodiments of master and slave devices and methods for operating the same.
BRIEF DESCRIPTION OF FIGURES
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
FIGS. 1A and 1B illustrate prior art signaling systems;
FIG. 2 illustrates a signaling system according to an embodiment of the present invention;
FIG. 3 is a timing diagram for the signaling system of FIG. 2;
FIG. 4 is a block diagram of a slave device according to one embodiment;
FIGS. 5A and 5B are a diagram of the operations performed by a master device to calibrate the internal transmit clocks of a plurality of slave devices;
FIG. 6 illustrates an iterative comparison of a test bit sequence and a captured bit sequence;
FIG. 7 illustrates the content of a phase array generated during slave device timing calibration;
FIGS. 8A and 8B are a diagram of the operations performed by a master device to calibrate the internal receive clocks of a plurality of slave devices;
FIG. 9 is a diagram of slave device responses to calibration commands from a master device;
FIG. 10 illustrates a circuit that may be included within a slave device to provide configurable clock cycle delay;
FIG. 11 illustrates the content of a two-dimensional phase array generated during slave device timing calibration;
FIG. 12 is a block diagram of a master device according to one embodiment;
FIG. 13 illustrates an exemplary computer system in which the master-slave system of FIG. 2 may be applied; and
FIG. 14 illustrates an alternative embodiment of a master-slave system.
DETAILED DESCRIPTION
Single Clock, Strobeless Signaling System
FIG. 2 illustrates a signaling system 30 according to an embodiment of the present invention. The system includes at least one master device 31 coupled to each of a plurality of slave devices 33 via a high-speed signaling path 37. The
high-speed signaling path 37 may be multiplexed for transmission of data and control information between the master and slave devices, or a separate path (not shown) may be provided for control information. A clock generator 35 generates clock signals
(CLK) that are delivered to the master device and each of the plurality of slave devices via respective clocklines 39. Though shown as a discrete component, the clock generator 35 may alternatively be incorporated into the master device 31. Preferably,
each of the slave devices 33 and the master device 31 are implemented in separate integrated circuit packages that are mounted to a printed circuit board, and the clocklines 39 and high-speed signaling path 37 are implemented by electrical traces
disposed on or within the printed circuit board. Alternatively, the entire signaling system 30 may be implemented within a single integrated circuit or within two or more integrated circuits disposed within a single integrated circuit package. Also,
though the master device 31 and slave devices 33 are shown connected to the clock generator 35 via respective clocklines 39, a single, shared clockline may alternatively be used to deliver a clock signal to the system components. An master-slave system
that includes such a shared clockline is described below in reference to FIG. 14.
Still referring to FIG. 2, the electrical lengths of the clock lines 39 are not constrained to be the same as the electrical length of the high-speed signaling path 37, and the signaling system 30 does not include paths for source synchronous
timing references as in the prior art systems described above. Instead, a timing calibration operation is performed at system startup to determine the respective data flight time delays between the master device 31 and each slave device 33. This flight
time delay is manifested within each slave device 33 as transmit and receive phase offsets relative to the externally received clock signal, CLK. Clock generation circuitry within the slave device 33 generates internal transmit and receive clock signals
that are offset from the external clock signal according to the transmit and receive phase offsets determined at system startup. Using this timing scheme, data transmitted to a given slave device 33 by the master device 31 is received under timing
control of the slave device's internal receive clock, and data transmitted from a slave device 33 to the master device 31 is transmitted under timing control of the slave device's internal transmit clock. Both data reception and transmission are timed
at the master device 31 by the external clock signal, CLK (or a clock signal generated therefrom). In contrast to the prior art systems described above, no source synchronous timing reference is required for transmissions in either direction. By using
a clock generator 35 that exhibits negligible frequency drift over changes in temperature (e.g., a high-precision crystal oscillator), receive and transmit clock phase offsets, once determined, remain valid over extended periods of operation.
System Timing
FIG. 3 is a timing diagram for a double data rate implementation of the signaling system of FIG. 2 (i.e., two bits of information are transmitted sequentially on the high-speed signaling path per cycle of CLK). A slave clock signal 44 (i.e., the
external clock signal received by the slave) leads a master clock signal 43 by an arbitrary phase angle, .phi.. As shown by master data transmit signal 45, a sequence of data values is transmitted by the master device, with the start of each successive
data eye (A, B, C, D) coinciding with a respective edge of the master clock signal 43. The data values arrive at the slave device after a flight time on the high-speed signaling path as indicated by slave data receive signal 46. The data flight time
may be expressed as a phase offset, .theta., where .theta.=(data flight time/clock period) * 360.degree.. Receive clock signal 47 is generated within the slave device and used to time reception of the receive data signal 46. In one embodiment, the
phase of the receive clock signal 47 is controlled such that edges of the receive clock signal coincide with the center of the data eyes (A, B, C, D) in the slave data receive signal 46. Thus, the phase relationship between the slave receive clock
signal 47 and the slave clock signal 44 may be expressed analytically as slave receive clock signal=slave clock signal +.phi.+.theta.+90.degree.. By sampling the incoming data in response to the edges of such a receive clock signal, maximum or near
maximum timing margin is achieved.
Still referring to FIG. 3, a data signal 48 to be received by the master device preferably arrives at the master device such that the data eyes (W, X, Y, Z) are centered around the edges of the master clock signal 43, regardless of which slave
transmitted the data. Assuming for simplicity that the flight time on the high-speed signaling path is the same in each direction, then the phase of the data signal as it departs from the slave device (i.e., signal 49) leads the data signal at the
master 48 by phase angle .theta.. Assuming further that edges of the slave's internal transmit clock signal are used to time the start of each data eye (W, X, Y, Z), the phase relationship between the slave transmit clock signal 50 and the slave clock
signal 44 may be expressed analytically as slave transmit clock signal=slave clock signal +.phi.-.theta.-90.degree..
Preferably, the phase of the internal receive clock of the slave device is advanced somewhat to compensate for the setup delay of the slave receive circuitry, and the phase of the internal transmit clock of the slave device is advanced to
compensate for the output delay (clock-to-Q delay) of the slave transmit circuitry. Such delays are accounted for in the timing calibration operations described below.
Note that while zero phase alignment between transmit clock and data and is assumed throughout this description (i.e., clock edge occurs at start of data eye), such phase alignment is not necessary. Any fixed phase relationship between transmit
clock and data may be used in alternative embodiments. Moreover, the fixed phase relationship between the slave transmit clock and data may be different from the fixed phase relationship between the master transmit clock and data.
Slave Device
FIG. 4 is a block diagram of a slave device 33 according to one embodiment. The slave device 33 includes three major functional blocks: input/output circuitry 61, timing circuitry 63 and application circuitry 65. The input/output circuitry 61
includes transmit circuitry 69 to transmit information supplied by the application circuitry 65 on the high-speed signaling path 37 and receive circuitry 71 to receive information via the high-speed signaling path 37 and forward the information to the
application circuitry 65. Transmit and receive clock signals (TCLK, RCLK) generated by the timing circuitry 63 are supplied to the transmit circuitry 69 and the receive circuitry 71, respectively, to time transmit and receive operations.
The application circuitry 65 varies according to the system in which the slave device 33 is to be used. For example, if the slave device 33 is a memory device in a memory system, the application circuitry 65 will include an array of memory cells
and circuitry to access contents of the memory cells in response to address and command information (i.e., control information) received via the receive circuitry 71. In such an application, data to be written to the memory cells is received via the
receive circuitry 71, and data read from the memory cells is transmitted to a system master (e.g., a memory controller) via the transmit circuitry 69. As discussed above, the high-speed signaling path 37 may include separate sets of conductors for the
data and control information, or the data and control information may be time multiplexed. Similarly, the internal data/control path between the receive circuitry 71 and the application circuitry 65 may include a separate sets of conductors for data and
control information or a single path may be time multiplexed. A separate external status path may likewise be provided and the internal data/status path between the application circuitry 65 and the transmit circuitry 69 may also include separate sets of
conductors for data and status information or a single path may be time multiplexed. If a separate external control path (or status path) is provided, a separate clock signal may be generated to time receipt (or transmission) of information on that
path. Such a clock signal may be operated at a different frequency from RCLK and TCLK.
The timing circuitry 63 includes receive timing circuitry 73 and transmit timing circuitry 79 for generating the receive and transmit clock signals, respectively (i.e., RCLK and TCLK). The receive timing circuitry 73 includes a delay lock loop
or phase lock loop (DLL/PLL) 74, a phase offset register 77 and a phase offset circuit 75 to offset the phase of the receive clock signal generated by the DLL/PLL 74 according to the content of the phase offset register 77. More specifically, a phase
offset value in the phase offset register 77 is applied to offset the phase of RCLK relative to the reference clock signal, CLK, such that RCLK and CLK have the relationship shown in FIG. 3 for signals 44 and 46. As discussed below, the phase offset
value in register 77 is set during a receive timing calibration operation to establish the appropriate phase offset between RCLK and CLK. The transmit timing circuitry 79 includes a transmit DLL/PLL 80 to generate TCLK, and a phase offset register 83
and phase offset circuit 81 to offset the phase of TCLK relative to CLK such that TCLK and CLK have the relationship shown in FIG. 3 for signals 44 and 50. The phase offset value in register 83 is set during a transmit timing calibration operation to
establish the appropriate phase offset between TCLK and CLK. As discussed below, the application circuitry 65 includes a calibration state machine 85 for responding to calibration commands from the master device. Slave responses to calibration commands
are discussed in detail below, but generally involve transmission and reception of test sequences on the high-speed signaling path 37, and modifying the contents of the transmit and receive phase offset registers 83, 77. Out-of-band communication
circuitry 87 is used to support out-of-band communication with the master device, and to forward calibration commands received via out-of-band communication to the calibration state machine 85. As discussed below, out-of-band communication may take
place via unused codespace on the high-speed signaling path 37 or via a separate slave device interface to initialization control path 67. Initialization control path 67 may be any connection between the slave device 33 and the master device that
permits communication outside the high-speed signaling path. For example, in one embodiment, initialization control path is a serial path that originates at the master device 31 and is daisy chained to each of the slave devices in the system (i.e., the
slave device interface to the initialization control path 67 includes a serial input which routes the signal carried on one conductor within path 67 to the out-of-band communication circuitry 87, and a serial output which supplies a signal output by the
out-of-band communication circuitry 87 to another conductor within path 67, the serial output of one slave device being coupled to the serial input of another slave device).
The dotted arrow leading to the calibration state machine 85 signifies use of the receive circuitry 71 to receive calibration commands after the phase offset of RCLK has been set.
Still referring to FIG. 4, numerous circuits may be used to offset the phases of the RCLK and TCLK signals relative to CLK based on the contents of the receive and transmit phase offset registers. For example, U.S. patent application Ser. No.
09/421,073, which is hereby incorporated by reference in its entirety, illustrates several techniques for providing offset in a slave DLL/PLL, including replication of phase offset blocks from the DLL/PLL reference loop to allow register-weighted phase
mixing of vectors from the replicated blocks to produce a desired phase delay (althoug | | |
