Methods, apparatus, and computer program product are provided for designing logic scan chains for matching gated portions of a clock tree. A clock tree includes a plurality of sections, each section including a gate receiving inputs of a global clock and a chain-specific clock control signal for a particular scan chain. A plurality of scan chains is defined, each including a plurality of latches. Each scan chain latch is connected to a corresponding chain-specific clock tree section.

A method of inspecting a mask or reticle, the mask or reticle being provided with a pattern to be transferred onto a semiconductor wafer, the pattern having a defect, includes the step of creating a plurality of logical zones and uniquely associating each of said logical zones with a surface area of said pattern. Then, an inspection rule representing a characteristic sensitivity for detecting a defect is associated with each of said logical zones. An image of said pattern is then recorded and compared with a reference image of an ideal pattern for locating a defect within said pattern. One of said logical zones is then identified with said located defect and that inspection rule which is associated with said identified logical zone is retrieved from a memory. The inspection rule is then applied to a characteristic of said defect for determining, whether said defect is to be repaired. A signal can be issued in response to said determination.

A technique for testability of a semiconductor integrated circuit is disclosed. In a first step, a fault simulation is conducted based on a predetermined test pattern to discriminate detectable faults and undetectable faults from each other. In a second step, undetected faults are listed. In a third step, the test conditions for the undetected faults are determined. In a fourth step, a test pattern most likely to meet the test conditions is selected from among a plurality of test patterns. In a fifth step, the registers associated with the undetected faults are replaced with scan registers, while at the same time connecting the scan registers in a scan chain to thereby make up a modified circuit. In a sixth step, a fault simulation is conducted by switching to the test condition at the timing corresponding to the undetected faults using the test pattern for the modified circuit.

A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.

A structure and method for identifying a physical location of a defect in a logic circuit based on a physical location of a logic latch having failing data. The logic circuit includes a plurality of logic latches, each having a predetermined physical location within the logic circuit. The logic latches are connected to devices adjacent the logic latches, such that the failing data in the logic latch indicates a failure of a device adjacent the logic latches.