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High speed linear feedback shift register
   
Document Number
US Patent 6654439
Issued Date
November 25, 2003
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Inventors
Kommrusch; Steve (Fort Collins, CO)
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Abstract
An apparatus and method for providing a high speed linear feedback shift register is disclosed. The high speed linear feedback shift register of the present invention comprises multiplexer flip flop circuits. The multiplexer gate on the input of each flip flop circuit is the only gate between each pair of flip flop circuits of the present invention. The linear feedback shift register of the present invention is capable of operating as a counter that does not need to be reset. The linear feedback shift register of the present invention may be used as a clock divider circuit.
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High speed linear feedback shift register - US Patent 6654439 Drawing
Drawing from US Patent 6654439
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Number of Claims:
16
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Published
November 25, 2003
Application Number
09/873,512
Filed
June 4, 2001
US Classification
377/54   377/77 377/80 377/81
Int'l Classification
H03K   23/66   (20060101)   H03K   23/00   (20060101)   H03K   23/54   (20060101)  
USPTO Field of Search
377/54   377/77   377/80   377/81  
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The shift register, which is an n-th shift register of a shift register chain, includes a first multiplexer, a second multiplexer, and a latch block, wherein n is a positive integer. The first multiplexer selects one of output data of the (n-1)-th shift register or output data of the (n+1)-th shift register and outputs the selected data to be used as a reset signal in the latch block. The second multiplexer selects one of the output data of the (n-1)-th shift register or the output data of the (n+1)-th shift register and outputs the selected data to be used as input data of the latch block. The latch block stores the output data of the second multiplexer in response to the clock control signal, the inverted clock control signal and the reset voltage, and outputs the stored data.

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