 |
Description  |
|
|
FIELD OF THE INVENTION
The present invention relates to the field of memory devices. Specifically, embodiments of the present invention relate to methods and systems for programming a memory device.
BACKGROUND ART
Presently, electronic memories come in a variety of forms and serve a variety of purposes. For example, one type of memory is flash memory. Generally, flash memories are used for non-volatile, fast information storage in devices such as digital
cameras and home video consoles. Flash memory may be considered a solid state storage device.
In general, flash memory is a type of electrically erasable programmable read-only memory (EEPROM). It has a grid of columns and rows with a cell that has one of two transistors at each intersection. One of the transistors has a floating gate.
When the floating gate has a neutral or positive net charge stored it conducts and the cell has a value of one. To change the value to a zero a process called Fowler-Nordheim (FN) tunneling is utilized.
FN tunneling is used to alter the placement of electrons in the floating gate. For example, a voltage is applied to the control gate above the floating gate and drain to the ground. This electric field causes the floating-gate transistor to act
similar to an electron gun. That is, the electrons are pushed through and trapped on the other side of the TOX layer, giving it a negative charge. These negatively charged electrons act as a barrier between the control gate and the floating gate. A
cell sensor then monitors the level of the charge passing through the floating gate. If the flow through the gate is greater than 50 percent of the charge, then it has a value of one. However, when the charge passing through the gate drops below the 50
percent threshold, the value changes to zero. Normally, a blank EEPROM has all of the gates fully open, giving each cell a value of one.
The electrons in the cells of a flash-memory can be returned to a normal state (e.g., one) by the application of an electric field (e.g., a higher voltage). Furthermore, flash memory utilizes in-circuit wiring to apply the electric field either
to the entire chip or to predetermined sections known as blocks. This electrical field erases the target area of the chip, which can then be rewritten. Therefore, flash memory works much faster than traditional EEPROMs because instead of erasing one
byte at a time, it erases a block or the entire chip. In addition, flash memory is non-volatile and as such it will maintain its data without an external source of power. Thus, it is extremely useful with removable memory media such as digital cameras,
digital music players, video consoles, computers, and the like.
Generally speaking, EEPROMs generate high voltages to induce electrons to move on and off of a floating gate in a metal oxide semiconductor field effect transistor (MOSFET) which charges the transistors threshold voltage. By changing the voltage
that effects the threshold of the device one can effect the current that will flow through it when it is powered. Logic one or zero can be determined by sensing the amount of current that can flow through the transistor at a given control gate voltage.
The electrons are free to move with no actual physical connection to the gate. So what is needed is an induction of the electrons to get them to move on or off of the poly-silicon electrode. This is done by applying high voltage to nodes that
are near the floating gate. For example, a high voltage may be applied to the drain, source, or in some cases an extra gate electrode located nearby. Electrons move either because they are ballistic (e.g., high energy) or they tunnel due to quantum
effect. In both cases, they move on and off the floating electrode. In flash technology, quantum tunneling is used. However, the electrons may be moved by ultraviolet light (UV) or X-ray.
The key is to get the right number of electrons on or off the electrode. However, since there is no way to touch the electrode, there is no way to measure the exact number of electrons thereon. Thus, the number of electrons thereon must be
inferred based on the variations of the current flow through the transistor of a programmed device. If too many electrons are on or off the device, early failure of the device may occur. In addition, there may be degradation in the current flow. Thus,
to maximize reliability, better control of the number of electrons actually placed on the device is needed.
Currently, the voltages are generated by a voltage pump that applies an electric field for a certain period of time during the memory programming process. Thus, by controlling both voltage and time, a basic statistical inference can be made with
regard to the amount of electrons that will be moved. Then, the device can be tested for the correct current flow parameters. For example, a statistical process may be used to define a number of volts and a time period for applying the voltage that
will result in correct programming.
Thus, for a specific manufacturing process, a publication by the manufacturer may state a voltage of 10 volts needs to be applied for 10 milliseconds to ensure proper operation or device programming. However, there are many statistical
variations within such a method, and therefore deleterious effects may result within the device depending on the environment in which programming occurs. Moreover, in order to resolve the reliability of the published voltages and times, a further trial
and error process is typically done to ensure that the correct current is indeed passing through the device. Such excessive testing may be both monetarily inhibiting and time consuming.
SUMMARY OF INVENTION
Thus, a need exists for an improved method for programming a flash or other non-volatile memory device. A further need exists for a method for programming a flash memory device, which can apply the most efficient programming voltage and
programming time for a specific memory device. A further need exists for a method for programming a memory device which can proficiently utilize the memory device temperature when calculating the most efficient programming voltage and programming time
for a specific memory device. Still another need exists for a method for programming a memory device which is compatible with existing memory device programming processes.
A method for programming a memory device is disclosed. In one method embodiment, the present invention receives a measurement from a temperature sensor located near a memory to be programmed. Next, a pre-existing transformation is
electronically accessed. Then, the measurement from the temperature sensor is processed in conjunction with the transformation which provides a programming time for a memory device as a function of a programming voltage and the temperature. The
programming voltage is then applied to the memory device for the length of time specified by the programming time in order to properly program the memory device. In one embodiment, the memory device is flash memory.
In one exemplary system, a host computer system downloads data to a programmable device to be programmed. The programmable device contains a programmable memory array, a voltage pump, a pulse width generator, a temperature sensor, a controller,
and a transformation as described above. The controller accesses the transformation based on the current temperature reading from the sensor. Programming voltage and pulse width data supplied from the transformation are provided to the charge pump and
pulse width generator. Memory programming then commences using techniques known in the art.
In one embodiment, the present invention is implemented in a microcontroller included on a single substrate. The microcontroller includes a microprocessor, a plurality of internal peripherals, an interconnecting component, an external coupling
port, and a memory for storing instructions. The microprocessor processes information. The plurality of internal peripherals are programmably configurable to perform a variety of functions associated with the microcontroller. The interconnecting
component is programmably configurable for selectively interconnecting the plurality of internal peripherals and other internal microcontroller components. The external coupling port is programmably configurable to implement different connectability
states by which the electronic system is connectable to an external device. The memory stores instructions and data (e.g., a configuration image) directed at setting the configurations and functions allocated to the plurality of internal peripherals,
the interconnecting component and the external coupling port.
In one embodiment of the present invention, the configuration and functionality of an electronic device is defined by a configuration image programmed in a memory of the electronic device. The configuration image includes instructions and data
for implementing the configuration and functions. In one embodiment, a plurality of configuration images facilitate dynamic reconfiguration of a programmable system on a chip (PSOC). In one exemplary implementation of the present invention, a
configuration image includes user module personalization data (e.g., PSOC configuration table), module parameterization data, application program interface (API) data, and user program code. Based upon the existence of a predetermined condition, the
PSOC is automatically reconfigured by activating different configuration images. In one embodiment, activating different configuration images results in different values being loaded in configuration registers of functional circuit blocks included in
the PSOC.
The present invention provides, in various embodiments, methods for programming a memory device. Embodiments of the present invention also provide a method for programming a memory device, which can calculate the most efficient programming
voltage and programming time for a specific memory device. The present invention further provides a method for programming a memory device, which can proficiently utilize the memory device temperature when calculating the most efficient programming
voltage and programming time for a specific memory device. The present invention also provides a method for programming a memory device, which is compatible with existing memory device programming processes.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 is a block diagram of an exemplary memory device in accordance with an embodiment of the present invention for programming a memory device.
FIG. 2 is a block diagram of an exemplary system for programming a memory device in accordance with an embodiment of the present invention.
FIG. 3 is a block diagram of an exemplary system for programming a memory device in accordance with another embodiment of the present invention.
FIG. 4 is a flowchart of steps performed in accordance with one embodiment of the present invention for programming a memory device.
FIGS. 5A, 5B, 5C, 5D, 5E, and 5F are exemplary graphs used to vary both the erase and program pulse widths as a function of temperature in accordance with an embodiment of the present invention.
FIG. 6 is a block diagram showing a high level view of an exemplary integrated circuit (e.g., a microcontroller) upon which embodiments of the present invention may be implemented.
FIG. 7A is a block diagram of one embodiment of a PSOC functional component depicted in greater detail.
FIG. 7B is a block diagram of one embodiment of a functional block, included in one exemplary implementation of a present invention functional block.
FIG. 8 is a flow chart of a PSOC dynamic configuration method, one embodiment of the present invention.
FIG. 9 is a flow chart of a PSOC design tool process illustrating exemplary steps used by a design tool in accordance with one embodiment of the present invention.
FIG. 10 is a table of exemplary variable definitions in accordance with one embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that
they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the
appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention may be practiced
without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.
Some portions of the detailed descriptions which follow are presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations on data bits within an electronic computing device and/or memory system.
These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. A procedure, logic block, process, etc., is herein, and
generally, conceived to be a self-consistent sequence of steps or instructions leading to a result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these physical manipulations take the form
of electrical, magnetic, optical or audio signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system or similar electronic computing device. For reasons of convenience, and with reference to common
usage, these signals are referred to as bits, values, elements, symbols, characters, terms, numbers, or the like with reference to the present invention.
It should be borne in mind, however, that all of these terms are to be interpreted as referencing physical manipulations and quantities and are merely convenient labels and are to be interpreted further in view of terms commonly used in the art.
Unless specifically stated otherwise as apparent from the following discussions, it is understood that throughout discussions of the present invention, discussions utilizing terms such as "transmitting", "receiving", "offsetting", "creating", "storing",
"delivering", "accessing", "generating", "providing", "processing", "outputting", "returning", "applying" or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data.
The data is represented as physical (electronic) quantities within the computing device's registers and memories and is transformed into other data similarly represented as physical quantities within the computing device's memories or registers or other
such information storage, transmission, or display devices.
With reference now to FIG. 1, in one embodiment, during the programming of a memory device such as memory device 100, the effects of temperature are utilized in conjunction with voltage and time to more optimally program the device.
Specifically, during the programming of memory device 100, tunnel effects such as Fowler-Nordheim (FN) tunneling may be temperature sensitive. Therefore, the amount of time that a programming voltage is applied is not a constant amount but in fact
temperature dependent. Thus, to program memory device 100, three variables are taken into account. The three variables are time, voltage, and temperature. Programming with accurate charge is desirable because under programming leads to data corruption
and over-programming may consume too much time as well as lead to data corruption.
The memory device described herein may be any type of non-volatile memory. In one embodiment, memory device 100 may be a flash memory device. Furthermore, memory device 100 may comprise control gate 101, floating gate 102, source 104, drain
106, oxide 105, tunnel oxide (TOX) 108, and P-well 120. In addition, memory device 100 may be a portion of a programmable electronic device, e.g., a microcontroller programmable system on a chip (PSOC). A more detailed description of a microcontroller
PSOC will be covered in more detail herein.
With reference now to FIG. 2, a block diagram of an exemplary system 200 for programming a memory device is shown in accordance with one embodiment of the present invention. In one embodiment, FIG. 2 is comprised of integrated circuit 205,
external computing system 210, bus 215, processor 220 of integrated circuit 205, temperature sensor 230 of integrated circuit 205, voltage pump 240 of integrated circuit 205, clock (pulse width generator) 250 of integrated circuit 205, memory device 270
of integrated circuit 205, and transformation 280 of integrated circuit 205.
In one embodiment, external computing system 210 may be a host system, e.g., a PC (personal computer), a mobile computing system, or the like, that may send data to be transferred into memory device 270. Bus 215, processor 220, and memory device
270 may be a multiplicity of computing devices and structures such as those discussed in more detail herein. For example, memory device 270 may be a flash memory device. Furthermore, in one embodiment, processor 220 may be a microprocessor. In
addition, integrated circuit 205 may be a microcontroller PSOC. The temperature sensor 230 may be on-chip or it may be external to integrated circuit 205.
Temperature sensor 230 may record or supply the current temperature of memory device 270, and/or integrated circuit 205, and/or ambient air temperature around memory device 270 and/or integrated circuit 205. For example, temperature sensor 230
may be utilized for measuring the temperature proximal to memory device 270. Temperature sensor 230 may also be a fixed constant temperature value at which the system is known to operate. Voltage pump 240 may be a device that can generate a specified
voltage based on a programmable input value. In one embodiment, voltage pump 240 may be able to generate only a fixed voltage. In another embodiment, voltage pump 240 may be able to generate a variable range of voltages based on a programmable input
voltage value. Pulse width generator 250 may be any type of clock (analogue or digital) that may be utilized to generate a pulse width, or a certain number of pulse widths. For example, clock 250 may be a programmable pulse width generator.
In one embodiment, transformation 280 is a memory table which has a time column 288, a voltage column 285, and a temperature column 282 containing variables. Moreover, transformation 280 is programmed with information pertinent to a particular
memory device 270 at manufacture. For example, when a memory device 270 is manufactured, a test may be run on the device to determine its optimal characteristics (e.g., programming time as a function of temperature and voltage, programming voltage as a
function of temperature and time, or programming temperature as a function of voltage and time). These optimal characteristics are then stored as data in the transformation 280. It is appreciated that the data stored in transformation 280 may be a
simple look-up table, such as that described above, or may contain constants of factors for equations used to calculate parameters (as described in FIG. 3). Thus, when memory device 270 needs to be programmed, the optimal voltage and duration of voltage
application based on a given temperature may be referenced from transformation 280. Transformation 280 may be stored on non-volatile memory such as ROM or a pre-programmed flash, or any other memory device such as those described herein. Additional
description of the initial testing of the device is described in more detail herein.
Referring still to FIG. 2, in one embodiment, external computing system 210 sends a request via bus 215 for processor 220 to place data into memory device 270. Upon reception of the request, processor 220 begins the programming process for
memory device 270. Initially, processor 220 accesses temperature sensor 230 of integrated circuit 205. Temperature sensor 230 then supplies a measurement of the temperature of memory device 270 to processor 220. In another embodiment, temperature
sensor 230 may constantly supply the temperature measurement to processor 220. In addition, although temperature sensor 230 is stated as measuring the temperature of memory device 270, temperature sensor 230 may measure any of the components of or
around integrated circuit 205.
Upon reception of the temperature measurement from temperature sensor 230, processor 220 accesses transformation 280. Processor 220 then uses the temperature provided by temperature sensor 230 as an index to transformation 280 which provides a
programming time for memory device 270 as a function of programming voltage and temperature. If voltage is a fixed amount, then the transformation 280 supplies only a programming time. Otherwise, the transformation 280 may provide a programming time
based on an input temperature and voltage. If only temperature is provided and voltage is not fixed, then the transformation 280 will provide an optimal voltage and programming time for that voltage.
Referring still to FIG. 2, processor 220 then accesses voltage pump 240. As stated herein, voltage pump 240 is utilized to apply the programming voltage to memory device 270. In one embodiment, voltage pump 240 is controlled by processor 220.
For example, voltage pump 240 may be a programmable voltage pump that can produce a range of voltages. Thus, processor 220 may program the voltage to be produced by voltage pump 240 based on a voltage data output from transformation 280. In another
embodiment, voltage pump 240 may only produce one voltage.
After establishing the parameters of the voltage output of voltage pump 240, processor 220 may complete the programming process of memory device 270 by supplying the appropriate programming time (as provided from transformation 280) to clock 250. For example, with the temperature and voltage defined, processor 220 may utilize transformation 280 (e.g., programming time 288 as a function of both voltage 285 and temperature 282) to establish the optimal time for which memory device 270 should
receive the voltage pulse. This programming time is then programmed into the pulse width modulator 250.
Referring still to FIG. 2, when the pulse width and voltage are programmed, the voltage is then applied to memory device 270 for the specified pulse width duration to program memory 270 with data simultaneously supplied in digital form from the
host device 210 over bus 215. For example, processor 220 may program a specific pulse width into clock 250. Clock 250 then allows volt pump 240 to provide memory device 270 with the optimal voltage for the specified pulse length to program the data.
Due to the preprogrammed transformations, memory device 280 is not over-programmed and therefore not over-stressed. In general, over-programming results in additional stress being placed on memory device 270 resulting in longer programming cycles, a
shorter life span, inefficient programming, or the like. Further, the memory is not under-programmed. In general, under-programming results in corruption of the data being stored.
With reference now to FIG. 3, a block diagram of an exemplary system 300 for programming a memory device is shown in accordance with another embodiment of the present invention. In general, system 300 operates in a similar fashion to system 200. However, as shown in FIG. 3, the plurality of parts utilized by system 300 may not necessarily be within integrated circuit 205. For example, in system 300 only memory device 270 and temperature sensor 230 are integral within integrated circuit 205. In
addition, transformation 280 of system 300 has an equation based format.
Furthermore, in system 300, transformation 280 (shown in one embodiment comprising equation 320, but may be a table as shown in system 200) may be located external to memory 270, e.g., coupled with external computing system 210. Moreover,
transformation 280 may be external as well, e.g., stored in a memory device such as read access memory (RAM), read only memory (ROM), flash memory, or the like, which may or may not be located on external computing system 210.
Referring still to FIG. 3, in one embodiment, the processor utilized for accessing transformation 280 may be integrated with external computing system 210. Thus, external computing system 210 may utilize the temperature provided by temperature
sensor 230 in conjunction with transformation 280 to establish a programming time for memory device 270 as a function of a programming voltage and temperature equation (or set of equations). In another embodiment, external computing system 210 may
utilize the temperature provided by temperature sensor 230 in conjunction with transformation 280 to establish a programming voltage for memory device 270 as a function of a programming time and temperature equation (or set of equations).
External computing system 210 may utilize bus 215 to program and control voltage pump 240, thereby providing the voltage for programming memory device 270. Furthermore, external computing system 210 may program pulse width modulator 250 for
regulating the time that the voltage will be applied to memory device 270 during programming.
Although two configurations of the system for programming a memory device are shown, it is appreciated that the arrangement of each portion of both system 200 and system 300 may are exemplary. Furthermore, the present invention is well suited to
a multitude of possible configurations.
With reference now to FIG. 4, a flowchart of steps performed in accordance with one embodiment of the present invention is shown. In one embodiment, the processes described herein, for example, in-flowchart 400, are comprised of computer
readable and computer executable instructions which reside in data storage resources of a computer system. The computer system includes, for example, non-volatile and volatile memory, a bus, and a processor. Further, the computer-readable and
computer-executable instructions are used to control, or operate in conjunction with, the processor.
Referring now to step 401 of FIG. 4, in one embodiment a measurement is accessed from a temperature sensor near a memory device. As stated herein, the measurement may be received by a processor such as the microprocessor portion of a PSOC, or an
embedded processor coupled with a computing system. In addition, the measurement may be received due to a request for the measurement from an outside device, as part of a regularly scheduled data burst, or the like. Moreover, the temperature sensor may
measure the temperature of a memory device, of a location proximal to the memory device, or of the ambient air around the memory device.
Referring still to step 401 of FIG. 4 and FIG. 2, in one embodiment a transformation is accessed. Transformation 280 is pre-programmed based on the specific memory device 270 with which it is coupled and contains data for a number of different
programming environments. In one embodiment, transformation 280 has time 288, voltage 285, and temperature 282 variables. In another embodiment, transformation 280 may have only time 288 as a function of temperature 282 with a constant voltage 285
assumed. In yet another embodiment, transformation 280 may have only voltage 285 as a function of temperature 282 with a constant time 288. In another embodiment, transformation 280 may contain equations that can be utilized by processor 220 to
calculate the programming voltage and time constraints.
With reference now to step 402 of FIG. 4 and FIG. 2, transformation 280 is indexed with the measurement from temperature sensor 230 to access a programming time for a memory device based on a programming voltage and temperature. In one
embodiment, the processing is performed by processor 220 of integrated circuit 205. For example, processor 220 may establish a programming time 288 for memory device 270 as a function of a programming voltage 285 and temperature 282. In another
embodiment, processor 220 may be a microprocessor PSOC. In yet another embodiment, processor 220 may be completely separate from integrated circuit 205. At step 403, the pulse width modulator is programmed and the voltage pump may be programmed.
Referring now to step 403 of FIG. 4 and FIG. 2, programming voltage 285 is applied to memory device 270 for the length of time specified by programming time 288 to program data into memory 270. For example, processor 220 utilizes voltage pump
240 to supply the programming voltage for memory device 270. Furthermore, processor 220 utilizes clock 250 to ensure the correct programming time for applying the programming voltage occurs. In one embodiment, clock 250 is a pulse width clock of
integrated circuit 205.
With reference now to FIGS. 5A-5F, a description of the process used to vary both the erase and program pulse widths as a function of temperature is shown in accordance with an embodiment of the present invention. Initially, an entire array or a
single block along a word line is first put into the erased state. From this state the other states of data 0 or data 1 may be obtained. One field-effect transistor (FET) may remain erased and the other may remain programmed. It is the single erased
FET that is sensed. The erase state may utilize a pulse duration between 1 and 20 ms depending on the high voltage pump output (Vpp), temperature and process corner. The write states utilize similar pulse durations.
Repeated erase operations at any given pulse width, on an erased FET causes that FET's threshold voltage to first decrease, but over many erase operations to eventually increase. This lowers the current available for read sensing and after some
large number of cycles (10K to 100K) there is insufficient current and the device fails to function during read. Repeated program operations raise an enhancement device's threshold, which fortunately is a beneficial effect.
As temperature increases the walkup of the erase threshold accelerates. Fortunately the duration of pulse to achieve a proper erased state decreases as temperature increases. These two effects aid each other. In fact, first order cancellation
of threshold walkup can be achieved by controlling pulse width.
As temperature decreases the walkup of erase or program thresholds decrease, however, the effectiveness of an erase or programming action decreases, requiring longer pulse widths.
In one example, the erased device is designed and characterized around a Vs=1.8 V @25 C. The main result is that device currents are lower that models predict, Vds is smaller so the bit line speeds are lower.
In general, a related gate voltage is used when an erased device in a flash memory has Ids exceeding a small reference current (e.g., just turns on). This voltage is called the erase margin voltage, and is sensed in the flash memory during
special test modes. It is possible to measure the margin voltages of any erased FET in the entire array (as well as the margin voltage of any Programmed FET also).
The PSOC devices have some features that allow for good control over the flash memory's programming. In one embodiment, these include independent 0.25 ms resolution and ranges from 1.0 ms to 20 ms over both the erase and program pulse widths.
Secondarily, the Vbg (band-gap reference that regulates the Vpp pump voltage) is trim-able over a +/-10% range, while maintaining a 2% accuracy. In addition, characterization data for dynamic control of the programming process can be stored into easily
accessible tables that are available to E.sup.2 emulation APIs (Application Programming Interfaces).
With reference now to FIG. 5A, in one embodiment flash table 500 is used for one exemplary temperature adaptive programming process. However, the erase curves (e.g., graph 550 of FIG. 5C) need to represent values in the units that the built in
flash hardware understands. Therefore, the time units may not be milliseconds (ms), but instead clockrates. For example, a clockrate of 90 represents 10.006 ms.
Referring now to graph 525 of FIG. 5B, a pulse width vs. clockrate graph shows one exemplary relationship between actual pulse width and the clockrate count parameter passed to the flash system calls. The following equations perform scaling
utilizing the following variables. (T) is temperature in units of degree `Celsius/128`; (M) is erase slope from FIG. 5A applicable to <0 or >=0 temperature range (unsigned char); and (B) is erase intercept from FIG. 5A applicable to <0 or >0
temperature range (unsigned char). Thus, the equation to perform the scaling is:
In one embodiment, the `.times.2/256` and temperature units allow 8-bit math to work efficiently and with maximal resolution. The `.times.2` is a 1 bit shift, and the `/256` is a memory index, this saves having to divide by 128 which is much
slower.
With reference now to FIG. 5C, the slope of the curves in graph 550 are always negative, but for ease of reading and dynamic range the M values are stored as positive numbers and their product with temperature is subtracted from the intercept.
In addition, the program multiplier in FIG. 5C represents a [0.5 to 2.0) multiplier encoded in a single unsigned byte in the range [32,127] that is later divided by 64 to get the scaling. This operation is performed as follows:
Referring still to FIG. 5C, two linear curves are used in graph 550 to represent two possible temperature ranges. An industrial temperature range (e.g., -40 to 100) will be covered by two lines, connected at zero degrees Celsius (C), while a
commercial temperature range (e.g., 0 to 100) will be shown as a single line. In one exemplary embodiment, the process desires the user to know the junction temperature of the device being programmed (e.g., memory device 270). Furthermore, in one
embodiment, only the curves for erasing memory device 270 will be stored, and the programming pulse will be derived by scaling the erase curves by a simple multiplier for each temperature range. In another embodiment, the programming pulse widths are
stored and are usually greater or equal to the erase pulse widths at any given temperature.
With reference now to FIG. 10, Table 10 is a description of the variable terms utilized herein.
Referring now to FIG. 5D, graph 570 shows saturation voltage versus pulse width for an exemplary case. In one embodiment, the ideal pulse width can be determined based on the erase margin saturation curve for each die. That is, Vem and Vpm
margin voltages reach saturation levels after a small integral pulse width, and greater pulse widths are increasingly less effective. Therefore, a minimum pulse width is utilized to reduce cycling stress while at the same time providing adequate charge
storage so that data is retained.
In one embodiment, by starting from a known programmed state (6 cycles of erase, data 1, erase, data 0): Vem decreases rapidly then saturates to some low value (near 1.00V). This saturation value increases due to endurance cycling. By
determining a pulse width for erasing that just brings a cell near saturation without excessive erasing, the number of cycles available for endurance may be maximized while still achieving full retention specs. In addition, by tracking the erase
saturation curve for each die the effects of process variation and Vpp pump variations are fully compensated for. Therefore, there is no need to measure or track Vpp voltages during programming.
In one embodiment, by measuring each die's erase saturation curve at 25 C and 100 C an ideal erase pulse width may be determined, and recording the linear curve equation data, into flash ROM tables that are accessible to user firmware for E.sup.2
emulation. By utilizing empirical experimental/characterization, the values for the program pulse widths can be extrapolated from the measured erase pulse widths. The 25 C data may be determined during factory manufacturing testing, while the 100 C
data may be determined via characterization.
The erase saturation data may be taken at -40 C, 0 C, 24 C, and 85 C forced ambient temperature. One embodiment of an exemplary testing model is shown below. 1) Cycle a block 6 times (at 10 ms pulse widths) performing Erase, Data 1, Erase, Data
0 states to establish an equilibrium condition for the erase margin states. 2) Write an Erase State into a block using the next pulse width from a series of 10. 3) Measure the Erase Margin voltage. 4) Repeat 1 through 3 for the next pulse width in the
series. 1) Cycle a block 6 times performing Erase, Data 0, Erase, Data 1 states to establish an equilibrium condition for the Program Margin states. 2) Write an Erase State into all cells within the same block as 1) using a large pulse width (10 ms) 3)
Program Data 0 into the block using the next pulse width from a series of 10. 4) Measure the Program Margin voltage. 5) Repeat 1 through 4 for the next pulse width in the series.
With reference now to FIG. 5E, the beginning Vem and Vpm thresholds during each series will be consistently close to each other and the Vem will decrease as the pulse width increases. Graph 580 shows that the erase margin after the initial 6
cycles, recovers to the same level more or less after each iteration, independent of pulse width of the erase that follows. The previously programmed FET experiences a weakened erase action that is not as deep as the FET that goes from erase with a
program inhibit to being fully erased. This effect is generally detrimental.
Referring now to FIG. 5F, as temperature changes from cold to hot, the ease of Vem saturation increases. Therefore, one process for determining erase pulse width includes taking the weighted average of Vem.sub.(1) after equilibrium cycling of E
D0, E D1 states and the saturated erase margin Vem.sub.(2) : (Vem.sub.(1) +9*Vem.sub.(2))/10=Vem.sub.(x), and locating the pulse width on a die's Erase Saturation curve (per temperature) that would give this voltage Vem.sub.(x). This results in the
pulse width for the temperature so chosen.
Moreover, since the saturation effects follow a log time vs. voltage curve, another embodiment for predicting pulse width includes cycling the die to stress nitride (equilibrated), applying the shortest possible erase pulse and measure
Vem.sub.(0), applying 5.0 ms erase pulse and measure Vem.sub.(5), applying 50 ms erase pulse to saturate devices, measuring Vem.sub.(s), projecting a straight line from Vem.sub.(0) through Vem.sub.(5) to where it intersects the horizontal line at
Vem.sub.(s), and taking 33% of the X intercept (time axis) as the optimal pulse width.
With reference now to FIGS. 6-9, a detailed description of PSOC operation is provided. The PSOC block contains programmable memory which can be programmed according to the embodiments of the present invention described herein. Specifically,
with reference now to FIG. 6, a block diagram showing a high level view of an exemplary integrated circuit (e.g., a microcontroller) 610 upon which an embodiment of the present invention may be implemented. In one embodiment, integrated circuit 610
includes a communication bus 215, static random access memory (SRAM) 612, central processing unit (CPU) 220, flash read-only memory (ROM) 270, input/output (I/O) pin(s) 618 and PSOC functional component 625. Communication bus 215 is electrically coupled
to static random access memory (SRAM) 612, central processing unit (CPU) 220, flash read-only memory (ROM) 270, input/output (I/O) pin(s) 618 and PSOC functional component 625. Static random access memory (SRAM) 612 stores volatile or temporary data
during firmware execution. Central processing unit (CPU) 220 processes information and instructions. Flash read-only memory (ROM) 270 stores information and instructions (e.g., firmware). In one embodiment of the present invention, flash read-only
memory (ROM) 270 stores configuration image data. Input/output (I/O) pin(s) 618 provides an interface with external devices (not shown). PSOC functional component 625 is programmable to provide different functions and configurations.
It is appreciated that integrated circuit 610 is readily adaptable to include a variety of other components. In one exemplary implementation, integrated circuit 610 also includes a dedicated functionality internal peripheral component 617 which
is coupled to system bus 215 in addition to the PSOC functional component 625. In one embodiment, dedicated functionality internal peripheral component 617 includes temperature sensor 230. An optional test interface (TI) may be coupled to integrated
circuit 610 via a test interface coupler (TIC), which may be detachable, to perform debugging operations during startup and initialization of the integrated circuit. In one embodiment of the present invention, additional functions such as clocking and
power control are provided by a variety of components including a precision oscillator and phase locked loop (PLL), a voltage reference, a 32 kHz crystal oscillator (which may be utilized for a variety of applications such as calibration and
synchronization, etc.), an interrupt controller (for generating interrupt signals as needed), a power on reset control unit (for performing functions related to power supply stability), and a brown-out detection unit (which detects substandard,
subnominal power system parameters).
Referring now to FIG. 7A, an embodiment of PSOC functional component 625 is depicted in greater detail. In this embodiment, PSOC functional component 625 includes an analog functional block 730, a digital functional block 740, and a programmable
interconnect 750. In one exemplary implementation, analog functional block 730 includes a matrix of interconnected analog functional blocks A1 through AN. The number N may be any number of analog functional blocks. Likewise, digital block 740 includes
a matrix of interconnected digital functional blocks D1 through DM. The number M may be any number of digital functional blocks.
The analog functi | | |
