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This application claims benefit and priority of Korean Patent Application
No. 2001-76944, filed Dec. 6, 2001.
BACKGROUND OF THE INVENTION
Conventional integrated circuits include a variety of active and passive
electrical components. The active electrical components may comprise,
e.g., diodes and transistors. The passive components may include, e.g.,
capacitors and resistors.
Integrated together upon a substrate, the electrical elements can provide
combined electrical functionality. For example, the integrated elements
might be used to provide memory as a dynamic random access memory (DRAM)
or static random access memory (SRAM). Additionally, a plurality of such
integrated memory chips may be assembled together to provide a memory
module of larger capacity memory.
Most memory modules use a plurality of integrated circuits mounted on both
sides of a module board, such as a printed circuit board. For example, a
plurality of memory chips--such as chip scale, gull wing, flip-chip, ball
grid array or other package configuration--may be mounted to opposite
surfaces of the module board. The board provides the physical support to
the integrated circuits. Additionally, it may electrically couple
terminals of the integrated circuits and external circuits.
A dual in-line memory module (DIMM) may comprise a plurality of memory
chips mounted to opposite surfaces of a printed circuit board. To
simplify, a wiring layout for the module board for chips that oppose one
another of the opposite sides may have pin assignments of mirrored
relationship. The chips for one side of the board may have terminals
(i.e., pins) of mirrored relationship relative to those of similar
identity on the opposite side of the board. Such mirrored chips may be
referred to as "mirrored pairs" or "mirror images."
When positioned opposite one another on opposite sides of a module board,
the terminals of same identity of the two opposing chips of a mirror may
be interconnected at substantially the same locations on the board.
Accordingly, the board layout may be simplified and the lengths of its
conductive traces may be kept short.
It may be understood that as the integrated circuit densities increase, the
integrity of interconnections and signal routing may be affected. The
increased densities may reduce line geometries, which in-turn may increase
circuit RC settling constants and propagation delays. Regardless,
manufactures continue to push for increased densities.
In addition to seeking greater densities, many manufactures strive to
provide for integrated circuit devices that may achieve substantially the
same propagation delays across a plurality of its interfaces--e.g.,
interfaces which may be associated with board-to-package transitions and
internal I/O lines of the device. If the electrical delays (i.e., lengths
or propagation paths) of the plurality of interfaces may be kept
substantially the same, device manufactures may be able to provide devices
of higher operating speeds and greater I/O capability than what might
otherwise be available. This may be especially valuable for development of
memory modules for multi-bit and synchronous data transfer applications.
SUMMARY
In accordance with an exemplary embodiment of the present invention, an
integrated circuit device comprises a substrate having circuitry
integrated together with the substrate. A switching circuit is selectably
operable to configure first and second signal paths of respective first
and second pads, the first and second pads of mirrored relationship about
an axis of the substrate. In accordance with a select signal, the
switching circuit may alternatively configure the first signal path
between the first pad and one node of first and second internal nodes, and
the second signal path between the second pad and the other node of the
first and second internal nodes. At least one of the first and second
signal paths may comprise a buffer positioned electrically in series
between the switching circuit and the respective first or second pad.
In a further exemplary embodiment, the buffer may comprise a signal
converter to convert signals of TTL levels to CMOS levels.
In another exemplary embodiment, the buffer may present an impedance match
to a transmission path associated with the first or second pad.
In yet a further aspect of an exemplary embodiment, a plurality of the
mirrored pair of first and second pads may be associated with
corresponding mirrored pins of a ball grid array.
BRIEF DESCRIPTION OF THE DRAWINGS
The present disclosure may be best understood with reference to the
accompanying drawings, wherein:
FIG. 1 is a schematic diagram of an underside of a ball grid array package
having a normal pin arrangement;
FIG. 2 is a schematic diagram of an underside of a ball grid array package
having a mirrored pin arrangement;
FIG. 3 is a schematic diagram of an arrangement of pads for a ball grid
array for a semiconductor integrated circuit device;
FIG. 4 is a schematic diagram of an integrated circuit device according to
an embodiment of the present invention;
FIG. 5A is a schematic diagram of a signal system showing external signals
to be applied to a package of a normal pin arrangement and also to another
package of a mirrored pin arrangement;
FIGS. 5B and 5C are partial cross-sectional views of a module board showing
opposing integrated circuits of a mirrored pair;
FIG. 6 is a schematic diagram illustrating a multiplexer for an exemplary
embodiment such as that as shown in FIG. 4;
FIGS. 7A to 7C illustrate exemplary embodiments of control circuits to
establish a select signal for driving the multiplexers of FIG. 4;
FIG. 8 is a schematic diagram of a routing structure which uses a package
of a mirrored pin arrangement according to an embodiment of the present
invention; and
FIG. 9 is a schematic diagram of an exemplary embodiment of the present
invention showing integrated circuits of a mirrored pair with bonding pads
and signal assignments such as those of row B in FIGS. 1 and 2.
DETAILED DESCRIPTION
In the following description, numerous specific details are set forth to
provide an understanding of exemplary embodiments of the present
invention. It will be understood, however, that alternative embodiments
may comprise sub-combinations of the disclosed exemplary embodiments.
Additionally, readily established circuits may be disclosed in simplified
form (e.g., block diagram style) to avoid obscuring the essence of the
embodiments with excess detail. Likewise, to aid a clear and precise
disclosure, the description of their operations--e.g., timing
considerations and the like--may similarly be simplified when persons of
ordinary skill in the art can readily understand their operations by way
of the drawings and disclosure.
"Substrate" or substrate assembly as used herein may be meant to include,
e.g., a die of a semiconductor wafer. Such die may have one or more layers
of material that have been formed on or within a substrate. The layers may
be patterned to produce devices (e.g., transistors, diodes, capacitors,
interconnects, etc.) for an integration of circuitry. In forming such
devices, the one or more patterned layers can result in topographies of
various heights. When referencing this integration of circuitry, it may be
described as being formed together, on or within the substrate and be
referenced as an "integrated circuit."
As used herein, "integrated circuit" may also reference the device after
further processing or fabrication for a given package configuration. The
package might be of a variety of configurations--such as, for example,
chip-scale, ball grid array, flip-chip, gull wing, J-lead, lead frame and
the like. Additionally, the integrated circuit may be referenced by
various sub-combinations of these terms--e.g., semiconductor integrated
circuit device or simply chip. In other words, through additional
packaging processes or fabrication, an intermediate level "integrated
circuit" may become an "integrated circuit" of a higher level of
realization.
The term "chip" may refer to a semiconductor die. Alternatively, it may
reference a type of "chip scale package" of, for example, a flip-chip
configuration. As used herein, its particular meaning will be clear in its
context of use.
With reference to FIG. 1, a ball grid array of an integrated circuit 150
comprises pins (e.g. 144 pins) 110 of various identifications of a first
signal assignment arrangement 100. In FIG. 1, exemplary identifications
for the pins 110 may be representative of signals to interface and operate
a memory device. The pins or pads of the array may be indexed by way of a
plurality of rows (A-M) and columns (1-12)--wherein, each pin/pad may be
referenced by a row, column index. For example, the bottom left pin may be
indexed as pin 110(A,1); the bottom row as pins 110(A); and the fourth
column as pins 110(4).
Certain pins of the array 100 may include an identification NC, see for
example, pins 110(F,2-3) and 110(F,10-11). The NC identification may
reference a terminal that may not be coupled internally. In the case of a
lead frame style package, the NC identification may indicate the absence
of a wire bond to the particular lead.
As used herein, "pins" may refer to terminals of an integrated circuit that
may interface an external circuit. In the case of a ball grid array, the
pins may comprise electrically conductive "balls" that are attached to
pads of the integrated circuit. Alternatively, the terminals may comprise
elevated or recessed conductive pads of the integrated circuit. The
elevated or recessed pads may electrically connect with mating sites of,
for example, a printed circuit board or other external circuit.
Referencing FIG. 2, integrated circuit 150' of a ball grid array
configuration comprises pins 110 having a pin-to signal arrangement 100'
that may mirror the first arrangement 100 of FIG. 1. The signals
identified for the arrangement 100' mirror those of the arrangement 100.
For example, pins 110(A,1) and 110(A,12) may be assigned identifications
of address bits A7 and A0 respectively within the array arrangement 100'
(FIG. 2); such assignments mirror the A0 and A7 assignments to the same
pins in arrangement 100 (FIG. 1). Thus, address A0 signal which is
transferred from memory controller is applied to address A0 pad 310(124)
of FIG. 3 through the pin 110(A, 1) in the normal pin arrangement (FIG.
1). On the other hand, the address A0 signal which is transferred from
memory controller is applied to address pad 310(90) of FIG. 3 through the
pin 110(A, 12) in the mirror pin arrangement (FIG. 2). However, the
address A0 signal which is applied to the address A7 pad 310(90) is
transferred to an internal circuit for address A0 signal through switching
circuit (MUX) in the mirror package.
Also, address A7 signal which is transferred from memory controller is
applied to address pad 310(90) of FIG. 3 through the pin 110(A, 12) in the
normal pin arrangement (FIG. 1). On the other hand, the address A7 signal
which is transferred from memory controller is applied to address pad
310(124) of FIG. 3 through the pin 110(A, 1) in the mirror pin arrangement
(FIG. 2). However, the address A7 signal which is applied to the address
pad 130(124) is transferred to an internal circuit for address A7 signal
through switching (MUX) in the mirror package.
In other words, both of pin 110(A, 1) of the FIG. 1 and pin 110(A, 12) of
the FIG. 2 receive an external address A0 signal generated from the memory
controller. However, the pin 110(A, 1) of the FIG. 1 is connected to an
address to an address pad 310(124) of FIG. 3 while the pin 110(A, 12) of
FIG. 2 is connected to an address pad 130(90) of FIG. 3 like 110(A, 12) of
FIG. 1.
Likewise, both pin 110(A,12) of FIG. 1 and pin 110(A,1) of FIG. 2 also
receive an external address A7 signal generated from the memory
controller. However, the 110(A,12) of FIG. 1 is connected to an address
pad 310(90) of FIG. 3 while the 110(A,1) of FIG. 2 is connected to an
address pad 310(124) of FIG. 3 like 110(A,1) of FIG. 1.
Even though the pin 110(A,1) of the FIG. 2 receiving an external address A7
signal is connected to the address pad 310(124) of FIG. 3, the external
address A7 signal is transferred to an internal circuit for A7 address
through the switching circuit (450) of FIG. 4 in response to SEL signal.
The reason why the pin 110 (A,1) of FIG. 2 receives address A7 is that the
pin 110(A,1) of FIG. 2 is located at the same position as the pin
110(A,12) of FIG. 1 when the normal pin configuration mounted a memory
chip and mirror pin configuration mounted a memory chip are packaged as a
chip package like FIG. 5a. Likewise, the reason why the pin 110(A,12) of
FIG. 2 receives an external address A0 is that the pin 110(A,12) of FIG. 2
is located at the same position as the pin 110(A,1) of FIG. 1 when two
kinds of pin configuration mounted a memory chip respectively are packaged
as a chip package like FIG. 5a.
Likewise, data bits DQS3 and DQS0 may be assigned to respective pins
110(M,1) and 110(M,12) of the arrangement 100', which in turn mirror their
alternative assignments in arrangement 100.
Thus, the pin-to-signal assignments to the arrangement 100' of FIG. 2 may
be described as mirroring the pin-to-signal assignments of the normal
arrangement 100 of FIG. 1. The descriptors "mirrored" and "normal" are
terms of convenience. It is understood that the arrangement 100 of FIG. 1
might be referenced as mirroring the normal arrangement 100' of FIG. 2.
Further referencing FIGS. 1 and 2, mirror axis 120 may be represented
across the integrated circuits 150 between the sixth and seventh columns
of pins 110(6) and 110(7). About mirror axis 120, the pin-to-signal
assignment of arrangement 100 (FIG. 1) mirrors that of arrangement 100'
(FIG. 2). Additionally, it may be observed that the placement of the pads
or pins 110 of integrated circuit 150 may physically mirror one another
about axis 120. For example, the physical placement of pin 110(A,6) may
mirror the physical placement of pin 110(A,7) about axis 120. And
similarly, the pins of other mirrored pairs may physically mirror one
another relative to axis 120.
In accordance with further embodiments, each pin of a mirrored pair may
comprise similar signal types. Referencing FIG. 1, the pins of the pair
110(A,1&12) may be assigned to address signals--e.g., A0 and A7
respectively; the pins of pair 110(A, 5&8) may be assigned to control
signals; the pins of pair 110(B,1&12) may be assigned to voltage signals
VREF; and the pins of pair 110(C,1&12) may be assigned to data signals
DQ23 and DQ8. Although, such similar signal assignments may be shown for
this embodiment, other embodiments may not necessarily maintain similar
signal type assignments (e.g., control signals, address signals, data
signals, and voltage signals) to respective pins of the mirrored pairs.
In general, it may be observed that the use of integrated circuits of
mirror image relationship can simplify the layout or routing of traces for
a module board, which may be viewed as supporting and electrically
interfacing the integrated circuits mounted thereon. Simplifying the
layout of traces for the board may improve the integrity of its channels
for signal propagation that may be used for channeling signals to various
pins of the mirrored pairs.
Absent such mirror image relationships, the electrical interfacing to the
pins of same identity for the different integrated circuits might,
therefore, require different traces of different electrical lengths. For
example, a trace (e.g., a conductive line on or within a circuit board) to
interface a pin of an integrated circuit on one side of the board may not
have the same length as that for a trace to a corresponding pin (of same
signal assignment) of an integrated circuit mounted on the opposite side
of the module. Such line length differences can degrade the integrity of a
signal destined to each of the pins.
For example, an address signal may reach the closer pin of a first
integrated circuit before reaching the same identity pin of the second
opposing integrated circuit. Such differences in time of arrival may have
an adverse impact to the overall memory module that may be trying to
implement synchronous-type data transfers or processing applications.
Additionally, the trace of shorter length may produce reflections that may
impact the quality of the signal that may also be destined to other
integrated circuits. Likewise, the longer length line may present an
undesirable impedance discontinuity where it meets a transmission line
associated with routing the signal to the closer integrated circuit. Such
discontinuity--e.g., such as where the two lines meet--likewise, can
adversely affect the quality of the signal to be received (or transmitted)
by the integrated circuits.
Various measures might be used to correct for the differences in signal
delays. For example, an addition of an extra line-length might be
incorporated with the shorter trace. But such extra length may demand more
board space. Additionally, it may increase its vulnerability to external
noise and, likewise, may allow signal transitions of the line to couple to
other regions of the module or radiate outside the module. Packages of
mirrored relationship may overcome some of these difficulties.
Referencing FIGS. 1 and 2, exemplary integrated circuits 100,100' of a
mirrored pair may comprise same arrangements of pads 110(A-M, 1-12).
Accordingly, the separate pins of opposing integrated circuits may be
coupled to a same signal line of the module board at substantially the
same locations on the board. This may avoid the need for different length
traces on the board for routing a signal to same identity pins of opposing
integrated circuits.
In accordance with exemplary embodiments of the present invention,
switching circuitry within an integrated circuit may be selectably
configurable to establish separate pad-to-signal assignments to pins of
the integrated circuit. This ability to configure the same integrated
circuit for different normal or mirrored pin-to-signal assignment may
allow the integrated circuit devices to be fabricated by same process
flows. Otherwise, the devices might require separate builds or process
flows for respective normal and mirrored configurations.
Referencing FIG. 3, exemplary integrated circuit 300 (alternatively,
substrate 300) of an intermediate level of fabrication may comprise pads
310 of an edge arrangement. The plurality of pads 310(1-166) may be
disposed along (i.e., proximate) an edge or outline 320 of the substrate.
Such configuration may be referenced as an "edge pad arrangement" or "edge
pad structure." With further processing or fabrication, the substrate 300
may receive additional re-routing lines to couple its edge pads 310 to
subsequently formed pins 110 of a ball grid array arrangement 100,100' of
FIGS. 1 and 2 respectively.
Further referencing FIG. 3, in accordance with exemplary embodiments,
internal circuitry of integrated circuit 300 may selectively and
alternatively route two different signals between different bonding pads
310 of integrated circuit 300. The different boding pad 310 of substrate
300 may be associated with respective mirrored pads 110 of ball grid array
configurations 100,100' (FIGS. 1-2). For example, an intermediate layer(s)
(e.g., such as semiconductor materials, dielectric, metal, vias etc.) may
form an interposer for establishing electrical links between a surface of
integrated circuit 300 (such as that shown in FIG. 3) and pins 110 of ball
grid array arrangements 100,100' of the integrated circuits 150,150'
(FIGS. 1 and 2).
In a particular exemplary embodiment, referencing FIGS. 1-3, bonding pad
310(90) of integrated circuit 300 for an address signal A7 may be
electrically coupled via an interposer layer (not shown) to pin 110(A,12)
of the normal ball grid array package 100 to receive an external address
A7. Similarly bonding pad 310(124) of integrated circuit 300 for an,
address signal A0 may be coupled to pin 110(A,1) of the normal ball grid
array package 100 to receive an external address A0.
For the mirrored configuration 100', on the other hand, the bonding pad
310(90) of integrated circuit 300 may be electrically coupled to pin
110(A,12) to receive an external address A0 along with the pin 110(A,1) of
FIG. 1. And, bonding pad 310(124) of substrate 300 may be electrically
coupled to pin 110(A,1) to receive an external address A7 along with the
pin 110(A,12) of FIG. 1 Selectively configurable circuitry internal the
integrated circuit, as will be described below, may determine the signal
associations of these, e.g., bonding pads 310(90),310(124) and pins
110(A,12),10(A,1).
In a memory module application, the pins for data, power and ground,
perhaps, may not need re-routing--i.e., between the mirrored and normal
arrangements. For example, as shown in FIG. 1, a supply Vss may be
assigned to pins of 110(D,5), 110(D,6), 110(D,7) and 110(D,8). Such signal
assignments may remain the same for both the normal and mirrored
arrangements. The same might be said for the data bits. Within memory
devices, the exact column locations of respective data bits to a given
word might not be of concern. Accordingly, the particular data bits of a
data word, as assigned to the pins of a package or IC, might not be
re-routed for the normal versus mirrored arrangements.
While data bits may not be mirrored for some embodiments; the exemplary
embodiments of FIGS. 1 and 2 on the other hand, establish arrangements
100,100' with mirrored data bit assignments. Mirroring of the data bit
assignments may be useful for enabling tight control of the timing
relationships for data transfers--e.g., as may be helpful for certain
high-speed or synchronous data transfer applications.
Address and control signals, in comparison to the data signals, will be
routed to predetermined internal circuits within the integrated circuit.
Without internal switching circuits to selectively configure these
internal circuits to receive designated signals of a normal or,
alternatively, a mirrored pin arrangement, unique interposer structures
might have been provided to re-route signals from a chip pad layout to
pins of a normal pin-out or, alternatively, to pins of a mirrored
arrangement.
Exemplary disadvantageous of these interposer structures may include, e.g.,
the need for separate process/fabrication flows to produce the separate
integrated circuits of the normal and mirrored interposer pin-out
arrangements. For example, the normal configuration and mirrored
configuration may comprise different interposers (not shown) to
electrically interconnect the chip bonding pads to pins of either the
normal or mirrored arrangement. But as the number of pins increase, the
re-routing circuits of the interposers may become more complicated.
Additionally, the electrical characteristics of semiconductor devices, with
such interposers may suffer as its frequency of operation (i.e., operating
speed) increases. With increases in operating frequency, differences in
I/O line lengths may become more pronounced. Accordingly, devices having
an interposer for establishing a mirrored pin-to-signal arrangement might
introduce signal delays to internal circuits that may be different from
the delays to the internal circuits for a device of normal pin-to-signal
arrangements. But for the present exemplary embodiments, internal
switching circuits that may be included to establish the alternative
signal assignments to the pins of an integrated circuit. Accordingly, the
interposer circuits can be eliminated, thereby, also eliminating some of
the interposer difficulties such as line length differences, signal
cross-couplings and noise vulnerabilities.
However, as operating frequencies continue to increase, some of the same
interposer-type considerations (line lengths, cross-couplings and noise
vulnerabilities) may, again, need to be taken into account in order to
maintain an operability of the integrated circuits and memory modules over
a wide range of operating frequencies.
Internal I/O lines of an integrated circuit may influence the integrity of
signals and signal propagation therein. To reach an internal circuit of an
integrated circuit, a signal may propagate, e.g., an I/O interface, a
first path from the I/O interface to a switching circuit, through the
switching circuit and along another path from the switching circuit to the
internal circuit. But just as a difference in electrical lengths between
interposers or board layout may influence the integrity of a signal
destined to internal circuits of normal and mirrored integrated devices,
so too may differences in internal paths of the integrated circuits also
affect signal integrity. Such differences may introduce some
problems--such as, e.g., variance in signal slew rates, miscorrelation of
signal transitions, inconsistent reflection characteristics,
discontinuities in impedance, propagation losses or unpredictable R/C
delays.
In accordance with an exemplary embodiment, with reference to FIG. 4, first
and second internal circuits 410,420 of an integrated circuit 150 may
receive signals of pads 430,440 or visa versa 440,430, respectively,
dependent on the selected state of switching circuit 450. In this
embodiment, switching circuit may comprise multiplexers 450A and 450B.
Multiplexer 450A may couple input 460A of the first internal circuit 410
to receive a signal of either pad 430 or pad 440 dependent on a control
signal of control line 470. Similarly (but complimentary to multiplexer
450A), multiplexer 450B may couple input 460B of second internal circuit
420 to receive a signal of either pad 440 or pad 430 dependent on the
control signal of line 470. Control circuit 480 may generate the control
signal for setting the configurations of multiplexers 450A, 450B.
Further referencing FIG. 4, buffers 490,496 may be disposed electrically in
series with the signal paths between the switching circuit 450 and pads
430,440 respectively. In accordance with one aspect of an exemplary
embodiment, the buffers may be positioned proximate to the I/O pads
430,440. For example, the length of transmission line 492 between pad 430
and associated buffer 490 may be less than several .mu.m. The length of
the transmission line 494 between the buffer and the switching circuit
450, on the other hand, may be greater than several .mu.m. For exemplary
embodiments, the buffers may be positioned electrically closer to the pads
than to respective switching circuits. In the illustrated embodiment,
buffer 496 may be position closer to pad 440 than to switching circuit
450.
In a further exemplary embodiment, the pads 430,440 may mirror each other
within an arrangement of a ball grid array (e.g., pads 110 of FIGS. 1-2).
In other embodiments, they may be disposed along an edge of a substrate of
an edge pad arrangement (e.g., pads 310 of FIG. 3). Additionally, an
interposer may couple the edge pads to mirrored pins of a ball grid array
package. In further embodiments, the edge pads may mirror one another
about a mirror axis over the substrate.
For a package of a normal arrangement, for example, multiplexer 450A may be
configured to couple the signal of pad 430 as buffered by buffer 490 to be
routed to the first internal circuit 410. Additionally, multiplexer 450B
may be configured to couple the signal of pad 440 as buffered by buffer
496 to the second internal circuit 420.
For establishing a mirrored arrangement, control circuit 480 may provide a
different control signal to line 470 and multiplexers 450A, 450B may be
reconfigured for the alternative configurations. Multiplexer 450A may
route the signal of pad 430 to the second internal circuit 420 and
multiplexer 450B may route the signal of pad 440 to the first internal
circuit 410.
In a further embodiment, buffers 490,496 comprise voltage converters. Each
may receive TTL levels from a source external the integrated circuit. The
buffers may convert the TTL level signals to CMOS levels that may drive
the internal circuits of the integrated circuit. When receiving the signal
form an external source, the signal may comprise a low level voltage that
may need buffering for used on-board the integrated circuit.
Additionally, a I/O signal path--e.g., 492 and 494-460A (or 494-460B)--from
the pad to the internal circuitry 410 (420) may cross or extend in close
proximity to other circuits of the integrated circuit. These other
circuits may provide signal transitions that may influence (by capacitive
or inductive couplings) signals of the I/O path. Such "noise"
cross-couplings to the I/O path may degrade signals destined for the
internal circuit(s). On the other hand, by buffering the signal paths
proximate the I/O pads, the buffers may provide greater drive capability
with levels more effective for propagation on-board the integrated
circuit. Additionally, the buffered signals may be less vulnerable to
noise cross-couplings or influences from neighboring circuits.
The buffers may also provide reverse isolation. Signals internal to the
integrated circuit (e.g., which may be of high levels relative to the
lower levels outside the integrated circuit) may, therefore, be kept
within the integrated circuit. Absent such buffers, the internal signals
that might be coupled onto the lines may propagate outwardly along the
lines to circuits external the integrated circuit. The buffers of the
signal paths, on the other hand, may provide reverse isolation for
attenuating the outward propagation of such (noise) signals along the
paths.
In the above exemplary embodiment, the buffers were described as buffering
signals from the I/O pads (e.g., 430,440) to be forwarded to the internal
circuits of the integrated circuit. It will be understood, however, that
the scope of the present invention encompasses other buffer orientations.
For example, the buffers might be oriented to receive signals of the
internal circuits and for outward propagation outwardly to the I/O pads
and external the integrated circuit. In such cases, the buffer may convert
the signal of the internal levels (e.g., CMOS) to an external level (e.g.,
TTL). Additionally, the buffer in this configuration may similarly provide
reverse isolation to prevent (noise) signals that may be external the
integrated circuit from propagating along the I/O signal path and into the
integrated circuit.
Further referencing FIGS. 1, 2, 4 and 5A-5C, semiconductor devices or
integrated circuits 150,150' of normal and mirrored pin-to-signal
arrangements 100,100' may be mounted on opposite sides of a board 510. In
this embodiment, mirrored pins (e.g., 110(K,5) and 110(K,8)) of the
respective integrated circuits 150,150' face each other and may be coupled
together by the board.
For example, board 510 may have mounting pads (e.g., | | |
