A method comprising forming a sacrificial layer over less than the entire portion of a contact area on a substrate, the sacrificial layer having a thickness defining an edge over the contact area, forming a spacer layer over the spacer, the spacer layer conforming to the shape of the first sacrificial layer such that the spacer layer comprises an edge portion over the contact area adjacent the first sacrificial layer edge, removing the sacrificial layer, while retaining the edge portion of the spacer layer over the contact area, forming a dielectric layer over the contact area, removing the edge portion, and forming a programmable material to the contact area formerly occupied by the edge portion. An apparatus comprising a volume of programmable material, a conductor, and an electrode disposed between the volume of programmable material and the conductor, the electrode having a contact area at one end coupled to the volume of programmable material, wherein the contact area is less than the surface area at the one end.
A memory device comprising a access circuits, an electrode layer over the access circuits, an array of phase change memory bridges over the electrode layer, and a plurality of bit lines over the array of phase change memory bridges. The electrode layer includes electrode pairs. Electrode pairs include a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. A bridge of memory material crosses the insulating member, and defines an inter-electrode path between the first and second electrodes across the insulating member.
The invention relates to a novel memory cell structure and process to fabricate chalcogenide phase change memory. More particularly, it produces a small cross-sectional area of a chalcogenide-electrode contact part of the phase change memory, which affects the current/power requirement of the chalcogenide memory. Particular aspects of the present invention are described in the claims, specification and drawings.
A method for manufacturing a memory device comprises forming an electrode layer on a substrate which comprises circuitry made using front-end-of-line procedures. The electrode layer includes a first electrode and a second electrode, and an insulating member between the first and second electrodes for each phase change memory cell to be formed. A bridge of memory material is formed on the top surface of the electrode layer across the insulating member for each memory cell to be formed. An access structure over the electrode layer is made by forming a patterned conductive layer over said bridge, and forming a contact between said first electrode and said patterned conductive layer.
A method for manufacturing a memory device uses a damascene process to define memory elements. The device comprises a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode and the top side of the second electrode. A damascene patch crosses the insulating member aligned with the first and second electrodes, and defines an inter-electrode path between the first and second electrodes across the insulating member. An array of such memory cells is provided.
A method of manufacturing for providing a narrow line, such as a phase change bridge, on a substrate having a top surface, includes first forming a layer of first material on the substrate. Then, a layer of a pattern material is applied on the layer of first material, and a pattern is defined. The pattern includes a ledge having a sidewall extending substantially to the layer of first material. A sidewall etch mask is formed on the ledge, and used to define a line of the first material on the substrate having a width substantially determined by the width of the sidewall etch mask.
