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System and method for efficiently performing data transfer operations
 
   
Document Number
US Patent 6678749
Issued Date
January 13, 2004
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Abstract
An apparatus and method for efficiently performing data transfer operations in an electronic system preferably includes a plurality of buffers that may store data and commands during execution of data transfer operations. Initially, at least a portion of a plurality of commands defining data transfer operations between a memory and peripheral devices may be temporarily stored in a command buffer associated with a processor interface. The processor interface may then issue commands directly to a memory interface, peripheral devices, and peripheral interfaces within the electronic system. Commands received by the memory interface may be temporarily stored in a command buffer associated with the memory interface. When a memory associated with the memory interface is ready, the memory interface may access the memory, and transfer data to or from one or more buffers associated with a peripheral device. Once the data is transferred to or from the buffers, then the memory interface may execute other commands stored in the command buffer. Execution of the first command does not have to be completed before the execution of a second command begins.
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Number of Claims:
24
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Owner
Sony Corporation (Tokyo,JP)
Sony Electronics Inc. (Park Ridge, NJ)
Published
January 13, 2004
Application Number
09/896,403
Filed
June 28, 2001
US Classification
710/5   710/18 710/52 712/225
Int'l Classification
G06F   3/00   (20060101)  
Examiner
Assistant Examiner
USPTO Field of Search
710/5   710/7   710/18   710/33   710/52   710/73   710/129   710/36   709/201   709/212   709/250   712/10   712/29   712/225  
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7577773 - Method and system for DMA optimization - Owned by QLOGIC, Corporation (Aliso Viejo, CA)

Method and system for processing read requests sent by a network interface device to a host system is provided. The method includes sending staggered read requests within a programmable time interval ("T"), wherein a transmit direct memory access (DMA) module sends more than one read request to the host system within the time interval T; placing data received from the host system in response to the read requests in independent slots of a transmit buffer; and unloading the transmit buffer slots based on an unload command, wherein the unload command is based on a mapping of read requests corresponding to transmit buffer slot locations where data from the host system is stored, and data is sent from the transmit buffer to a network device in the same order as the read requests that are sent from the network interface device to host system.

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Description
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