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| United States Patent | 6681293 |
| Link to this page | http://www.wikipatents.com/6681293.html |
| Inventor(s) | Solomon; Doug (Los Altos, CA), Eiriksson; Asgeir T. (Sunnyvale, CA), Koren; Yuval (San Francisco, CA), Kaldani; Givargis G. (Los Gatos, CA) |
| Abstract | A method and apparatus for purging data from a middle cache level without
purging the corresponding data from a lower cache level (i.e., a cache
level closer to the processor using the data), and replacing the purged
first data with other data of a different memory address than the purged
first data, while leaving the data of the first cache line in the lower
cache level. In some embodiments, in order to allow such mid-level
purging, the first cache line must be in the "shared state" that allows
reading of the data, but does not permit modifications to the data (i.e.,
modifications that would have to be written back to memory). If it is
desired to modify the data, a directory facility will issue a purge to all
caches of the shared-state data for that cache line, and then the
processor that wants to modify the data will request an exclusive-state
copy to be fetched to its lower-level cache and to all intervening levels
of cache. Later, when the data in the lower cache level is modified, the
modified data can be moved back to the original memory from the caches. In
some embodiments, a purge of all shared-state copies of the first
cache-line data from any and all caches having copies thereof is performed
as a prerequisite to doing this exclusive-state fetch. |
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Title Information  |
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Drawing from US Patent 6681293 |
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Method and cache-coherence system allowing purging of mid-level cache
entries without purging lower-level cache entries |
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| Publication Date |
January 20, 2004 |
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| Filing Date |
August 25, 2000 |
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| Parent Case |
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is related to a U.S. Patent Application entitled "CACHE
LINE CONVERTER," Ser. No. 09/650,101, filed on Aug. 25, 2000: a U.S.
Patent Application entitled "DRAM MICROPROCESSOR CACHE WITH ON-CHIP TAGS,"
Ser. No. 09/652,797, filed on Aug. 31, 2000; a U.S. Patent Application
entitled "METHOD AND CACHE-COHERENCE SYSTEM ALLOWING PURGING OF MID-LEVEL
CACHE ENTRIES WITHOUT PURGING LOWER-LEVEL CACHE ENTRIES," Ser. No.
09/650,100, filed on Aug. 25, 2000: and a U.S Patent application entitled
"MULTIPROCESSOR NODE CONTROLLER CIRCUIT AND METHOD," Ser. No. 09/407,428,
filed on Sep. 29, 1999, each incorporated herein by reference. |
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Title Information |
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