A method and apparatus are disclosed for reducing the complexity of reduced state sequence estimation (RSSE) techniques for a given number of states while also reducing the critical path problem. The intersymbol interference due to the less significant tail taps of the channel impulse response is processed with a lower complexity cancellation algorithm using tentative decisions, while the intersymbol interference due to the more significant initial taps is processed with a more complex cancellation algorithm, such as a reduced state sequence estimation technique or an M-algorithm technique. A receiver is disclosed that includes a circuit for processing intersymbol interference due to the less significant tail taps using tentative decisions and an RSSE circuit for processing the intersymbol interference due to the more significant taps.
A Reduced-State Sequence Estimation (RSSE) method is disclosed, whereby states in a trellis structure associated, for example, with a Viterbi algorithm are partitioned into a plurality of hyper-states. During a hyper-state decision interval, a hyper-soft value is calculated. The calculated hyper-soft value is a measurement of the accuracy of the hyper-state decision made. The calculated hyper-soft value can be used by an equalizer to generate soft-value information for decoding. A soft-value generated from such a hyper-soft value combined with bit soft-value in an RSSE algorithm is significantly more accurate than a soft-value that can be generated for a DFSE algorithm (i.e., without such a hyper-soft value).
A receiver (1) has an equalizer (2, 4, 5) which introduces inter symbol interferance (ISI) in a controlled manner and low pass filters to reduce noise. The ISI is introduced and the noise is reduced by a filter (4) in an adaptation path. A trellis decoder (3) of the receiver (1) removes the ISI to avoid propagation error. It does this in front end modules (20), outside of its critical path. There is a better decoder performance because noise is smaller.
Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
A method executed in a receiver that combines a decoder with an equalizer in a single module, comprising receiving at time k a signal r(k) in the receiver. Selecting as a signal transmitted by a transmitter a signal that minimizes the following equation metric .xi..function..function..times..function..times..function..times..functio- n..times..function. ##EQU00001## where {tilde over (h)}.sub.j(l) is related to both the transmission channel and to the encoding structure in the transmitter, {tilde over (s)}(k) is a trial symbol specified by a selected trellis transition and s(k) is a symbol that was previously decided. Applying the selected signal to the decoder to decode received symbols.
Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
