Disclosed is a method for forming bit line and bit line contact structure. Based on a semi-finished structure with a poly plug filled in a contact window, the method of the Invention comprises steps of removing some of the oxide layer so that the plug protrudes, oxidizing the exposed region of the protruding portion of the plug, removing the oxidized portion of the plug, forming a first dielectric layer to the upper surface of the resultant structure, wherein the upper surface of the plug is exposed, forming a second dielectric layer to the upper surface of the first dielectric layer including the upper surface of the plug, forming photoresist on the second dielectric layer, then performing exposing, developing and etching to form a trench of a predetermined pattern, and filling metal into the trench to form a bit line.

A static random access memory cell with metal fill to form capacitors for increasing the capacitance of the memory cell. More specifically, a semiconductor device including a structure having an upper surface and a contact surface formed at the upper surface of the structure. A dielectric material is formed over the contact surface with a first conductive node and a second conductive node extending beyond the dielectric material. Dielectric spacers are formed around the first and second conductive nodes and conductive elements are formed between the dielectric spacers. The conductive elements and spacers form capacitors without implementing additional masking steps.

A re-recordable data storage medium is disclosed. One embodiment of the medium includes a dielectric material and a filler material. The dielectric material is organized in columnar channels over which memory cells are logically distributed. The filler material is within the columnar channels to realize the memory cells. The filler material of each memory cell has at least a first configuration and a second configuration. The first configuration corresponds to a first storable logical value, and the second configuration corresponds to a second storable logical value.

The present invention relates to a process of forming a phase-change memory. A lower electrode is disposed in a first dielectric film. The lower electrode comprises an upper section and a lower section. The upper section extends beyond the first dielectric film. Resistivity in the upper section is higher than in the lower section. A second dielectric film is disposed over the first dielectric film and has an upper surface that is coplanar with the upper section at an upper surface.