In evaluating the location of a failure in a logic circuit including gates defined in a hierarchical manner, the present invention discloses a system capable of evaluating the location of a failure by referring to the circuitry of a gate described by a basic gate without creating any special databases that are dedicated to evaluating the location of a failure. In this system, expected value setting device obtains an expected value of a target gate inside the logic circuit by an IF-THEN operation in an output direction, logical state evaluating device obtains a logical state of the target gate inside the logic circuit by an IF-THEN operation in an input/output direction, and a failure propagation path inside the target gate is obtained by comparing the expected value with the logical state. Furthermore, temporary decided line retrieving device retrieves an input terminal of the target gate, a temporary logical value being set thereon, by referring to the circuitry of the target gate recorded in a logic circuitry storage unit, and the expected value and the logical state inside the target gate recorded in a logical state storage unit, and then related failure terminal setting device obtains a related failure terminal in the input/output terminal of the target gate by referring to the circuitry of the target gate recorded in the logic circuitry storage unit, and the expected value and the logical state inside the target gate recorded in the logical state storage unit, when no temporary decided lines are detected, and the target gate is determined to be an established gate.
A test method allows testing of source-synchronous high-speed wide busses on automatic testing equipment for at-speed characterization and production at-speed testing. An integrated circuit that is verified using the method and systems including such an integrated circuit are also disclosed. The invention can enable sampling or testing of signals or test pins that that are running very fast, particular compared to available automatic testing equipment for testing these device. The invention uses data recovery emulation on various types of automated test equipment to capture output data for further, more sophisticated analysis.
A method is disclosed for identifying a physical failure location on an IC without using layout-versus-schematic (LVS) verification tool. In the method, the integrated circuit is tested with one or more test patterns to identify a failure port thereon. Hierarchical information of the failure port is generated through the test patterns. A physical location of the failure port in a layout of the integrated circuit is identified through a relation between the hierarchical information and a floor plan report. Layout information of a routing path associated with the physical location of the failure port is retrieved from a layout database.
