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Method for forming isolation pattern in semiconductor device
   
Document Number
US Patent 6706617
Issued Date
March 16, 2004
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Abstract
A method enables a hole-type LPC mask to be employed instead of the conventional T-type LPC mask, thereby reducing time and manpower for the manufacture of the mask. The method comprises the steps of: arranging a plurality of bit lines at regular intervals in a longitudinal direction on a semiconductor substrate; arranging a plurality of gate lines at regular intervals in a transverse direction while intersecting the bit lines; forming isolation patterns on a semiconductor substrate, each of the isolation patterns having wing-like branches in a bent shape, each of the bit lines extending over and overlapping on central portions of the isolation patterns, each of the gate lines being in contact with side end portions of the isolation patterns; and forming first contact holes through the wing-like branches of each of the isolation patterns and forming a second contact hole through the central portion of each of the isolation patterns between the wing-like branches.
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Number of Claims:
11
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Owner
Hynix Semiconductor Inc. (Kyoungki-do,KR)
Published
March 16, 2004
Application Number
10/317,929
Filed
December 12, 2002
US Classification
438/453   257/E21.549 257/E21.577
Int'l Classification
H01L   21/70   (20060101)   H01L   21/762   (20060101)   H01L   21/768   (20060101)  
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Priority Data
Mar 13, 2002 [KR] 2002-13629
USPTO Field of Search
438/453   438/439   438/294  
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