Device and method for controlling solid-state memory system

It is claimed:

1. A mass storage system for use with a computer system, comprising:

a plurality of solid-state memory device chips, each having a large number of memory cells partitioned into individually addressable chunks for write or read operations, said memory cells being organized into one or more sectors individually addressable for erase operation;

a memory chip controller for controlling the plurality of memory chips, said memory chip controller being adapted to communicate with the computer system; and

a device bus for connecting said memory chip controller to each of said plurality of solid-state memory chips, said device bus carrying serialized address, data and command information, thereby substantially reducing the number of connections therebetween.

2. A mass storage system as in claim 1, wherein the memory chips are flash EEPROM devices.

3. A mass storage system as in claim 1, wherein the device bus includes two serial-in lines, two serial-out lines, a clock line, a master chip-select line, a serial protocol control line, and a plurality of power lines.

4. A mass storage system as in claim 3, wherein the memory chips are flash EEPROM devices.

5. A mass storage system as in claim 1, wherein the device bus consists of two serial-in lines, two serial-out lines, a clock line, a master chip-select line, a serial protocol control line, and a plurality of power lines.

6. A mass storage system as in claim 5, wherein the memory chips are flash EEPROM devices.

7. A mass storage system as in claim 1, wherein the mass storage system is adapted to communicate with the computer system via a standard computer system bus, and wherein the mass storage system is adapted to be powered by a standard power supply within the computer system.

8. A mass storage system as in claim 7, wherein the memory chips are flash EEPROM devices.

9. A mass storage system as in claim 1, wherein the mass storage system is adapted to communicate with the computer system via a standard computer bus interface, and wherein the mass storage system is adapted to be powered by a standard power supply within the computer system.

10. A mass storage system as in claim 9, wherein the memory chips are flash EEPROM devices.

11. A mass storage system as in claim 1, further including:

one or more backplanes each containing a plurality of mounts, each said plurality of mounts adapted to receive one of the plurality of memory chips;

an extension of the device bus to each of the plurality of mounts for connection to the memory chip thereon;

a set of device-select pinouts on each memory chip;

a set of corresponding pads on each mount for connection to the set of device-select pinouts of the memory chips mounted thereon, said set of corresponding pads having a predetermined configuration of grounded pads to define a mount address and therefore a unique array address for each memory chip mounted on each said one or more backplanes.

12. A mass storage system as in claim 11, wherein the memory chips are flash EEPROM devices.

13. A mass storage system as in claim 11, each said memory chip further including:

a device select circuit for enabling the memory chip thereof whenever ap array address received from the device bus coincides with the array address obtained from the set of device-select pinouts as defined by the predetermined configuration of grounded bonding pads.

14. A mass storage system as in claim 13, wherein the memory chips are flash EEPROM devices.

15. A mass storage system as in claim 13, said device select circuit further including:

means responsive to an asserting chip-select signal and a clock signal from the device bus for converting a serialized array address from the device bus to a corresponding parallel array address; and

means for asserting a memory chip-select signal whenever a match occurs between the corresponding parallel array address and the array address obtained from the set of device-select pinouts as defined by the predetermined configuration of grounded bonding pads.

16. A mass storage system as in claim 15, wherein the memory chips are flash EEPROM devices.

17. A mass storage system as in claim 13, wherein said device select circuit further including:

a master-select circuit for enabling the memory chip thereof whenever said set of corresponding pads are configured with a predetermined, master-select grounding configuration.

18. A mass storage system as in claim 17, wherein the memory chips are flash EEPROM devices.

19. A mass storage system as in claim 17, wherein the memory chip is enabled by said master-select circuit and a dedicated chip select signal.

20. A mass storage system as in claim 19, wherein the memory chips are flash EEPROM devices.

21. A mass storage system as in claim 11, wherein said device select circuit further including:

a device deselect circuit for disabling each memory chip thereof whenever an array address received from the device bus coincides with a predetermined address.

22. A mass storage system as in claim 21, wherein the memory chips are flash EEPROM devices.

23. A mass storage system as in claim 1, further including:

one or more memory submodules each containing a plurality of memory-device mounts, each memory-device mount adapted to receive one of the plurality of memory chips;

one or more backplanes each containing a plurality of submodule mounts adapted to receive one of the plurality of memory submodules;

an extension of the device bus to each memory submodule for connection to each memory-device mount and therefore to each memory chip thereon;

a set of device-select pinouts on each memory chip;

a set of corresponding pads on each memorydevice mount for connection to the set of device-select pinouts of the memory chips mounted thereon, said set of corresponding pads being partitioned into first and second subsets of pads;

said first subset of pads capable of providing group of grounded pads configurations to define unique addresses for all memory-device mounts and therefore addresses for corresponding memory chips mounted on each memory submodule; and

said second subset of pads being connected to corresponding pads on each submodule mount and capable of providing a second group of grounded pads configurations to define unique addresses for all submodule mounts and therefore addresses for corresponding memory submodules mounted on each backplane.

24. A mass storage system as in claim 23, wherein the memory chips are flash EEPROM devices.

25. A mass storage system as in claim 23, each said memory chip further including:

a device select circuit for enabling the memory chip thereof whenever an array address received from the device bus coincides with the array address obtained from the set of device-select pinouts as defined by the predetermined configuration of grounded bonding pads.

26. A mass storage system as in claim 25, wherein the memory chips are flash EEPROM devices.

27. A mass storage system as in claim 25, said device select circuit further including:

means responsive to an asserting chip-select signal and a clock signal from the device bus for converting a serialized array address from the device bus to a corresponding parallel array address; and

means for asserting a memory chip-select signal whenever a match occurs between the corresponding parallel array address and the array address obtained from the set of device-select pinouts as defined by the predetermined configuration of grounded bonding pads.

28. A mass storage system as in claim 27, wherein the memory chips are flash EEPROM devices.

29. A mass storage system as in claim 25, wherein said device select circuit further including: a master-select circuit for enabling the memory chip thereof whenever said set of corresponding pads are configured with a predetermined, master-select grounding configuration.

30. A mass storage system as in claim 29, wherein the memory chips are flash EEPROM devices.

31. A mass storage system as in claim 29, wherein the memory chip is enabled by said master-select circuit and a dedicated chip select signal.

32. A mass storage system as in claim 31, wherein the memory chips are flash EEPROM devices.

33. A mass storage system as in claim 23, wherein said device select circuit further including:

a device deselect circuit for disabling each memory chip thereof whenever an array address received from the device bus coincides with a predetermined address.

34. A mass storage system as in claim 33, wherein the memory chips are flash EEPROM devices.

35. A mass storage system as in claim 1, each said solid-state memory device further including:

a serial protocol logic for controlling the protocol of the serialized address, data and command information carried in the device bus, said serial protocol logic comprising;

means for routing and converting serialized addresses from the device bus to a parallel address bus;

means for routing and converting serialized data from the device bus to a parallel data bus;

means for routing and converting serialized command codes from the device bus to a plurality of parallel command lines;

a pointer shift register means for capturing a code from the device bus;

a pointer decode means for selectively enable said one of the routing and converting means; and

a serial protocol control signal from the device bus for enabling said pointer shift register means for capturing the code from the device bus while disabling said converting means, and for disabling said pointer shift register means after the code has been captured and enabling said routing and converting means.

36. A mass storage system as in claim 35, wherein the memory chips are flash EEPROM devices.

37. A method for transferring command, address and data information between two system via a serial bus connected therebetween, comprising the steps of:

serializing each command, address or data information into respective string components;

providing a code tag to each respective string component;

multiplexing the respective string components into a serial stream so that each respective string component has a definite start and end time sequence and is preceded by its corresponding tag code;

providing a serial protocol control signal which provides a time reference for the start and end of each respective string component in the serial stream;

transferring the serial stream and the serial protocol control signal from one system to another system;

detecting the start and end of each respective string component in the serial stream by reference to the serial protocol control signal;

reading,the tag code of each respective string component and routing each respective string component in the serial stream accordingly, thereby extracting each command, address or data string components from the serial stream in the other system.

38. A method as in claim 37, further comprising the step of:

converting each routed command, address and data information back to a parallel format.

39. In a memory system having at least one memory device in communication with a controller, said memory device transferring data with the controller serially, an improved method of reading data stored in the memory device, comprising the steps of:

reading a new chunk of data as a current chunk of data from the memory device in parallel;

converting the current chunk of read data from parallel to serial format and shifting out to the controller;

setting up the address for the next chunk of data to be read and sending it from the controller to the memory device while the current chunk of data is being shifted out from the memory device to the controller;

accessing the memory device with the address for the next chunk of data while the current chunk of data is being shifted out from the memory device to the controller; and

repeating all the above steps, after the current chunk has been shifted out of the memory device, until all chunks to be read have been shifted out of the memory device.

Description Submit all comments and votes

BACKGROUND OF THE INVENTION

This invention relates generally to a device and method for electronic data communication and particularly that between a memory controller and an array of memory chips.

Conventional memory system design uses a large number of parallel signals for the addressing, data transfer, and control of system operations. This is a very convenient means of configuring memory systems and results in very fast system operation. This is particularly true for integrated circuit, random access memory devices.

A disadvantage arises from this approach in that a large number of signal lines needs to be routed to each and every memory device in the memory system. This entails rather inefficient use of printed circuit board area and large cables and backplanes. Also, the system power supply must have higher capacity in order to deliver higher peak power for parallel signalling. In most cases, however, this inefficiency must be tolerated in order to achieve best possible speed of operation.

In some applications, on the other hand, it is possible to employ a serial link between two systems in order to reduce the number of cables therebetween, as well as the size of the cables, backplanes, and circuit boards in the systems. Overall, physical density can be dramatically improved over conventional methods, in that circuit boards can be made smaller and the total physical volume required for the connecting systems can be reduced. However, serial connections are usually slower than their parallel counterparts.

It is desirable to have simple connections between a memory controller and an array of memory devices, without compromising performance.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to simplify the connections between two systems with minimum compromise on performance.

It is another object of the present invention to simplify the connections between a controller and an array of solid-state memory devices.

It is another object of the invention to provide means and method for improvements in selecting one or more memory devices within the a memory array for communication.

It is also an object of the invention to provide means and method for de-selecting the improvements in deselecting memory devices which have previously been selected for communication.

It is yet another object of the present invention to allow the memory devices of the memory array to be configured so that they are all enabled for simultaneous communication.

It is yet another object of the present invention to improve the speed of the memory devices.

These and additional objects are accomplished by improvements in the architecture of a system comprising a memory controller and an array of solidstate memory devices, and the circuits and techniques therein.

According to one aspect of the invention, an array of solid-state memory devices are in communication with and under the control of a controller module via a device bus with minimum lines. This forms an integratedcircuit memory system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized and multiplexed before being transferred between the controller module and the memory subsystem. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. When the control signal is asserted, a circuit on each memory device of the subsystem interprets the serialized bits of information as a pointer code. After the control signal is de-asserted, deasserted, the each device routes subsequent bits of the serialized information to the appropriate command, address or data registers according to the type of information pointed to by the code.

The present invention uses a serial link to interconnect between the solid-state memory devices and the controller module. The serial link greatly reduces the number of interconnections and the number of external pads for each device, thereby reducing cost. Also expansion of the memory capacity of the system is simply achieved by a higher packing density of devices on standard printed circuit boards. It is not necessary to have a variety of circuit boards for each density, since the number of address and chip select signals does not change with capacity.

An important aspect of the invention is to employ a broadcast select scheme to select or enable a given memory device chip among an array of chips in a memory board or memory module. Each memory device chip has a multi-bit set of pinouts that is connected internally to a device select circuit and externally to a multi-bit mount on the memory module's backplane. Each multi-bit mount on the backplane is preconfigured pre-configured or keyed to a given address (represented by a multi-bit combination of "0"s and "1"s) according to its location in the array. In one embodiment, the terminals in the multi-bit mount corresponding to the "0" bit are set to ground potential. When a memory chip is powered on, the address of the array as defined by the mount key is passed onto the device select circuit of the chip. To select a given memory chip, the correct array address for that chip is sent to all the chips in the array via the interconnecting serial bus. This address is compared at each chip with that it acquired from its each chips mount, and the chip that matched is selected or enabled by its device select circuit. A memory chip remains selected until explicitly deselected, allowing more than one memory chip to be enabled at a time.

The invention provides a simple scheme for assigning an array address to each of the chips mounted on a memory module's backplane. By providing the keying at the backplane instead of at the memory chips, the memory chips can be made generic. This also avoids the need for conventional use of using conventional individual chip select to enable each memory chip. This results in very low pin count in multi-chip modules, especially that of socketed modules, enabling high density package packing of memory chips on memory modules.

According to another aspect of the invention, the array of memory chips may be distributed over a plurality of memory modules. Each of the memory modules can be enabled by a module select signal from the controller module.

According to another aspect of the invention, each memory module may be further partitioned into a plurality of memory submodules. These submodules may be mounted on a memory module's backplane and are all enabled by the same module select signal. The multi-bit address in the multi-bit mount for each memory device is partitioned into two subsets. The permutations of one subset are used to provide the different memory-device addresses on a memory submodule. The permutations of the other subset are used to provide the different memory-submodule addresses on a memory module. Thus, there is a pre-configured preconfigured multi-bit mount for each memory submodule on the memory module's backplane.

According to another aspect of the invention, one particular key among the permutations of the multibit mounts is reserved as a "master key" to unconditionally have each device select circuit enable its chip. In the preferred embodiment, this "master key" is given by having all the bits of a multi-bit mount not grounded. This allows a group of chips with this "master key" mount to be selected together.

According to yet another aspect of the invention, the broadcast select scheme has a reserved code that can be communicated to the array of memory chips on the backplane in order to deselect all previously selected chips. In the preferred embodiment, a select sequence of shifting in a pattern of all ones results in a global deselect.

Another important aspect of the invention is to implement a streaming read scheme to improve the read access of the memory system. While a chunk (e.g. 64 bits) of data is being read from the memory cells, serialized and shifted out of a memory chip, the address for the next chunk is being setup and sent to the memory chip to begin accessing the next chunk of data. The overlapping operations of reading out of one chunk of data and staging for the access of the next chunk of data greatly improve the read access speed of the memory system.

As mentioned before, the use of a serial link is unconventional for integrated circuit memory chips. These memory devices are typically random-access memories which are designed for high speed access and therefore employ parallel address and data buses. Serializing the command, address and data information for these devices is unconventional since it may require more circuitry than conventional parallel access, and may result in slower access. However, the present invention, when used in a block transfer regime (e.g., reading 4096 consecutive user bits at a time, is relatively insensitive to access time, the speed being determined largely by the data throughput once reading has begun. The present invention recognizes that employment of a serial link in the present EEPROM electrically erasable programmable read only memory ("EEPROM")system architecture, particularly with the features of broadcast selection and streaming read, results in simplified connections therein without compromising access speed for the intended application.

Additional objects, features and advantages of the present invention will be understood from the following description of the preferred embodiments, which description should be taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a general microprocessor system connecting connected via a bus interface to a solid-state mass storage system according to a preferred embodiment of the present invention;

FIG. 1B is a general microprocessor system connecting connected directly via a system bus to a solid-state mass storage system according to another preferred embodiment of the present invention;

FIG. 2A illustrates schematically the solidstate memory module having arranged as an array of memory devices mounted on "keyed" mounts in a memory board backplane;

FIG. 2B illustrates schematically another memory partition module arrangement in which a plurality of memory submodules are being mounted on "keyed" mounts on the backplane of the solid-state memory module, and a plurality of memory devices is being mounted on "keyed" mounts on each memory submodule;

FIG. 3 illustrates a "radial select" configuration of the memory devices in FIG. 2 in which the mounts all have the master, all-bits-ungrounded "keys", and each memory devices device is selected by an individual chip select (CS*) signal;

FIG. 4 is a schematic illustration of the functional blocks of a flash EEPROM memory device;

FIG. 5A shows one embodiment of the device select circuit within the memory device illustrated in FIG. 4;

FIG. 5B is a timing diagram for the device select circuit of FIG. 5A;

FIG. 6A is one embodiment of the serial protocol logic within the memory device illustrated in FIG. 4;

FIG. 6B is a timing diagram for the serial protocol logic of FIG. 6A;

FIG. 6C shows the logic state of signals in the device select circuit shown in FIGS. 4-6;

FIG. 7A is a schematic illustration of the functional blocks of the controller module illustrated in FIG. 1A;

FIG. 7B is a schematic illustration of the functional blocks of the alternative controller module illustrated in FIG. 1B;

FIG. 8A is a schematic illustration of the functional blocks of the memory controller illustrated in FIG. 7A;

FIG. 8B is a schematic illustration of the functional blocks of the memory controller illustrated in FIG. 7B; and

FIG. 9 is a timing diagram for the read streaming scheme, according to a preferred embodiment of the present invention.

Table 1 shows the logic of the device select circuit in FIGS. 4-6.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A typical computer system in which the various aspects of the present invention are incorporated is illustrated generally in FIG. 1A. A typical computer system 101 has an architecture that includes a microprocessor 121 connected to a system bus 123, along with random access, main system memory 125 (which may include read only memory (ROM) and random access memory (RAM)), and at least one or more input-output (I/O) devices 127, such as a keyboard, monitor, modem and the like. Another main computer system component that is connected to a typical computer system bus 123 is a large amount of long-term, nonvolatile memory 129. Conventionally, such a mass storage is a disk drive with a capacity of tens of megabytes of data storage. During the functioning of the computer system 101, data from this mass storage 129 is retrieved into the system volatile RAM of main system memory 125 for processing, and new or updated data can be easily written back to the mass storage.

One aspect of the present invention is the substitution of a specific type of semiconductor memory system for the disk drive but without having to sacrifice non-volatility, ease of erasing and rewriting data into the memory, speed of access, and reliability. This is accomplished by employing an array of non-volatile, solid-state memory, integrated circuit chips. This type of memory has additional advantages of requiring less power to operate, and of being lighter in weight than a hard disk drive memory, thereby being especially suited for battery-operated portable computers.

The integrated circuit mass storage memory 129 includes one or more solid-state memory modules such as 131, 132 under the control of a controller module 133. Addresses, data, and commands are communicated between the memory modules 131, 132 and the controller module 133 by means of a device bus 135. The one or more memory modules such as 131, 132 can be selectively enabled by individual module select signals such as MS1*, MS2*. These signals are carried in select lines such as 151, 152 from the controller module to individual memory modules. The controller module 135 is connected to a bus standard computer bus interface 137 via an interface bus 138. The interface 137 is connected on the other hand to the computer system via the standard computer system bus 123. The mass storage memory is adapted to be powered by a standard power supply within the computer system. For personal computer systems the bus interface 137 is preferably an IDE (Integrated Device Electronics) controller.

FIG. 1B illustrates an alternative embodiment in which the controller module 134 is connected directly to the system bus 123 of the computer system 101. In this embodiment, as will be described later, the controller module 134 is simplified as some of its functions are performed by the system microprocessor 121 and other system resources.

Solid-State Memory Module

FIG. 2A illustrates schematically the solidstate memory module such as 131 or 132 of FIGS. 1A and 1B having arranged as an array of memory devices 141 mounted on a printed circuit memory board or a backplane 143. Each memory device 141 is an integrated circuit memory chip.

Each memory device 141 has two groups of external pads or pinouts. The first group is the device-bus pinouts 145 for connection to the device bus 135 on the backplane 143. In this way, the device bus 135 interconnects between all the memory devices 141 in the solid-state memory module 131 on the one hand, and the controller module 133 or 134 on the other hand (see FIGS. 1 and 21A-1B and 2A-2B).

The second group of external pads are deviceselect pinouts 147 which are to be connected to corresponding pads of a mount 149 on the backplane 143. There is one such mount for each memory device so that the memory devices 141 are laid out in an array in the backplane 143.

As an example, a memory device 141 may have five device-select pinouts, which are connected to five corresponding pads on the mount 149. By selectively grounding certain pads, such as a pad 161 on the mount, each mount may be configured or "keyed" to designate a definite address of the array. With five pins, the number of groundable pad configurations or "keys" amounts to 25=32 permutations. Thus in the preferred embodiment, the mounts in the array will have grounding configurations (11111), (11110), (11101), (00000), where "0" denote a pad that is grounded.

As will be discussed in connection with a device select circuit illustrated in FIGS. 4 and 5A, these keyed mounts are used to assign an array address to the memory device chip 141 mounted thereon. In this way each memory device chip can be addressed for selection or enablement.

FIG. 2B illustrates schematically another memory partition module arrangement in which each memory module such as 131 may be further partitioned into a plurality of memory submodules such as 181, 182. This allows for more flexibility in memory configurations without the need to provide at the outset the full capacity of mounts for all possible memory devices 141 in the memory module's backplane 143. In this way, the backplane 143 needs only provide a reduced set of mounts and spaces for these submodules. Each submodule such as 181, 182 has a smaller group of memory devices 141 mounted on it and they are all enabled by the same module select signal MS1* 151.

Similar to the case illustrated in FIG. 2A, each memory device 141 is given an address on the memory submodule 181 by means of the grounding configuration of the multi-pin mount 149. However, with a reduced number the memory devices in a submodule, only a subset of the bits of the multi-pin mount is required. For example, with four memory devices 141 per submodule, only two bits of the multi-pin mount 149 need be configured to provide unique addresses on each submodule. The rest of the bits in the multi-pin mount 149 may be configured to provide unique addresses for the memory submodules such as 181, 182 on the backplane 143 of the memory module 131. For a 5-bit mount, two of the bits are configured for four memory-device addresses on each memory submodule, and the other three bits are configured for up to eight memory-submodule addresses on the memory module's backplane 143.

The memory submodules such as 181, 182 are each mounted on the memory module's backplane 143 with connections to the device bus 135 and to a submodule multi-pin mount 89. This mount 189 is a subset of a memory-device's multi-pin mount 149. For the example above, it will be a 3-pin mount.

According to another aspect of the invention, one particular "key" among the permations of grounding configurations of the multi-bit mounts 149 is reserved as a "master select" which unconditionally allows each chip to be selected or enabled.

FIG. 3 illustrates a radial select scheme, in which all the memory devices 141 in the solid-state memory module 131 can be enabled for selection by a "master-select" "master select" configuration. In the preferred embodiment, this "master select" is given by having all the bits of the mount not grounded. Thus, each mount 149 in the array has the same grounding configuration, namely (11111). Individual memory device devices within the solidstate memory module 131 is are selected by dedicated chip select signals such as CS1*, CS2*, CS31* in the conventional case. These dedicated chip select signals are respectively carried in additional lines such as 171, 172, 175 among the device bus 135.

Flash EEPROM Memory Device

Examples of non-volatile, solid-state memory, integrated circuit chips include read only-memory (ROM), electrically-programmable-read-only-memory (EPROM), electrically-erasable-programmable-read-only-memory (EEPROM), and flash EEPROM.

In the preferred embodiment, an array of flash electrically-programmable-read-only memories (EEPROM's) in the form of an integrated circuit chip employed as the memory device 141. A flash EEPROM device is a non-volatile memory array which may be partitioned into one or more sectors. These sectors are addressable for wholesale electrical erasing of all memory cells therein. Various details of flash EEPROM cells and systems incorporating defect managements management have been disclosed in two related co-pending U.S. patent applications. They are copending U.S. patent applications, Ser. No. 508,273, filed Apr. 11, 1990, by Mehrotra et al., now U.S. Pat. No. 5,172,338 and Ser. No. 337,566, filed Apr. 13, 1989, by Harari et al., now abandoned, and Ser. No. 963,838, filed Oct. 20, 1992, by Harari et al, now U.S. Pat. No. 5,297,148 which is a divisional application of Ser. No. 337,566. Relevant portions of these two disclosures are hereby incorporated by reference.

FIG. 4 is a schematic illustration of the functional blocks of a flash EEPROM memory device. The flash EEPROM memory device 141 includes an addressable flash EEPROM cell array 201, a device select circuit 203, a serial protocol logic 205, a power control circuit 207, and various WRITE, READ, ERASE circuits compare and shift register 211, 213, 215, 217 and 219.

Serial Device Bus

One important feature of the present invention is to employ a serial link between each of the memory devices 141 and the controller module 133 or 134. The serial link carries serialized addresses, data and commands. This has several advantages in the present application. The serial link greatly reduces the number of interconnecting lines between the controller module 133 or 134 and each of the memory devices chip 141. Fewer signal lines requires fewer traces on the printed circuit memory boards or backplanes 143, resulting in dramatic savings in board space and overall system density improvements. Fewer pins are required. This applies both to memory card edge connectors and to individual memory device chip pinouts. The results of fewer pins are is lower costs and greater system reliability. Also fewer pinouts on a memory device results in a smaller device and consequently, lower device cost. Finally, expanding the memory capacity of the system is simply achieved by a higher packing density of devices on standard printed circuit boards. It is not necessary to have a variety of circuit boards for each density, since the number of address and chip select signals does not change with capacity when employing a serial link. By having a common serial interface, a controller can be designed to support memory devices of differing capacities without modifications to the system. In this way, future memory devices of different capacities can be connected to the same controller without hardware changes resulting in forward and backward compatibility between memory cards and controllers.

Still referring to FIG. 4, the flash EEPROM memory device 141 has two sets of external pins. The first set of external pins is for connection to the device bus 135. The device bus 135 includes a timing signal line, CLK 231, a control signal line P/D* 235, two serial-In's, SI0237, SI1239, two serial-Out's, SO0241, SO1243, and a set of power lines V1 . . . Vn 245. Another control signal line, chip select CS* 171 is shown outside the device bus 135, although in some embodiments, it may be regarded as part of the device bus 135. The use of two serial-In's and two serial-Out's requires very few signal lines and yet still allow allows information to be transferred at adequate rates.

The second group of external pins consists of the five device-select pinouts 147 described in connection with FIGS. 2 and 3.

Device Select Scheme and Circuit

According to the present invention, any memory device 141 among the array of memory devices mounted on the backplane 143 may be enabled such that the device is selected whenever the CS* 171 (chip select) is asserted. In particular, each device may be enabled in one of two ways.

The first is "master-select" "master select" by means of a special grounding configuration of the device select pins 147, as described earlier in connection with FIG. 3. One particular "key" among the permutations of grounding configurations of the multi-bit mounts 149 (see FIG. 3) is reserved as a "master select" which unconditionally allows each chip to be selected or enabled. This allows a group of chips with this "master select" mount to be selected together (see FIG. 3A) or allows for radial selection of individual devices (see FIG. 3B).

The second is "address-select" by shifting in an address that matches the one defined by the device select pins 147 from the serial lines SI0237, SI1239. As described in connection with FIGS. 2 and 3, the address for each location in the array is defined by the grounding configuration or "key" of the mount 149 thereat. By virtue of the memory device connecting being connected to the mount 149, the address defined by the mount is passed onto the memory device 141. Whenever a memory device 141 is to be selected, its array address is made available on the device bus 135. A device select circuit in each memory device 141 compares the array address obtained from the device bus to that obtained from the device select pinouts 147.

According to yet another aspect of the invention, an "address-deselect" "address deselect" scheme is employed in which a special address or code can be shifted in to deselect devices that have previously been selected. In the preferred embodiment, the special deselect code is (11111).

Table 1 summaries FIG. 6C summarizes the logic states of signal of the device select circuit 203 which appears in FIGS. 4-6. The device select circuit has inputs from the device select pins 147 and the device bus 135, and has an output DS 309 (see FIG. 5A) to select or deselect the device it is controlling.

FIG. 5A shows one embodiment of the device select circuit 203 incorporating the "master-select" "master select", "address-select" "address select", and "address-deselect" "address-deselect" features. The circuit 203 has inputs SI0237, SI1239, and the two control lines CS* 171, P/D* 235 from the device bus 135. In the present example, the array address of the memory device 141 in FIG. 4 is defined by a 5-bit address. This 5-bit address is set by the mount 149 and communicated to the device select circuit 203 via the deviceselect device select pinouts 147.

The master-select master select feature is implemented by the 5-input AND gate 301. Wh