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Chip testing within a multi-chip semiconductor package    
United States Patent6732304   
Link to this pagehttp://www.wikipatents.com/6732304.html
Inventor(s)Ong; Adrian E. (Pleasanton, CA)
AbstractA system and method is provided for testing a secondary chip housed within a multi-chip packaged semiconductor device. The packaged semiconductor device includes a secondary chip and a primary chip, with the secondary chip communicating with the primary chip through signal drivers. The secondary chip also includes at least one test signal driver connected to the signal drivers and to certain external connectors that may be shared with the primary chip. The test signal drivers provide testing of the secondary chip using standard integrated circuit test equipment while the secondary chip is contained within the packaged semiconductor device.
   














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Drawing from US Patent 6732304
Chip testing within a multi-chip semiconductor package - US Patent 6732304 Drawing
Chip testing within a multi-chip semiconductor package
Inventor     Ong; Adrian E. (Pleasanton, CA)
Owner/Assignee     Inapac Technology, Inc. (San Jose, CA)
Patent assignment
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Publication Date     May 4, 2004
Application Number     09/666,208
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     September 21, 2000
US Classification    
Int'l Classification    
Examiner     Decady; Albert
Assistant Examiner     Gandhi; Dipakkumar
Attorney/Law Firm     Sidley Austin Brown & Wood LLP
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Patent Tags     chip testing within multi-chip semiconductor package
   
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Market Size
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> $10B
$5B - $10B
$2B - $5B
$500M - $2B
$100M - $500M
$10M - $100M
$1M - $10M
$500K - $1M
$100K - $500K
< $100K
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$0
 
$0   $2.5B   $5B   $7.5B   $10B
Market Share
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75% - 100%
50% - 74.99%
25% - 49.99%
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2 - 4.99%
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Reasonable Royalty
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5 - 9.99%
2 - 4.99%
1 - 1.99%
< 1%
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