Arrangement of integrated circuits in a memory module

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to memory modules for use in computers. More specifically, the invention relates to the layout and organization of SDRAM memory modules to achieve 1-Gigabyte (i.e., 1,073,741,824 bytes) or more capacity using standard TSOP integrated circuits.

2. Description of the Related Art

The demand for high speed, high capacity memory modules for use in the computer industry has grown rapidly. The average base memory capacity of servers recently increased from 512 Megabytes to 1.2 Gigabytes. The cost of dynamic random access memory (DRAM) modules declined by more than 75%.

To successfully operate in a computer, a memory module must meet standard timing and interface requirements for the type of memory module intended for use in the particular computer. These requirements are defined in design specification documents that are published by either the original initiator of the standard (e.g., Intel or IBM) or a standards issuing body such as JEDEC (formerly, the Joint Electron Device Engineering Council). Among the most important design guidelines for memory module manufactures are those for PC SDRAM, PC133 SDRAM, and DDR SDRAM. The requirements documents also provide design guidelines which, if followed, will result in a memory module that meets the necessary timing requirements.

To meet the requirements defined in the SDRAM design guidelines and respond to consumer demand for higher capacity memory modules, manufacturers of memory modules have attempted to place a higher density of memory integrated circuits on boards that meet the 1.75" board height guideline found in the design specifications. Achieving the effective memory density on the printed circuit board has presented a substantial challenge to memory module manufacturers. High memory density on the memory module board has been achieved via the use of stacked integrated circuits and the use of more compact integrated circuit connector designs, such as micro-BGA (Ball Grid Array)

Use of non-standard integrated circuits, such as micro-BGA integrated circuits increases costs. Micro-BGA integrated circuits use a connection technique that places the connections for the integrated circuit between the body of the integrated circuit and the printed circuit board. Consequently, micro-BGA integrated circuits can be placed closer to one another on a board than can integrated circuits using the more prevalent TSOP (Thin Small Outline Package) packaging techniques. However, integrated circuits using micro-BGA connectors typically cost twice as much as comparable capacity TSOP integrated circuits.

Stacking a second layer of integrated circuits on top of the integrated circuits directly on the surface of the printed circuit board allows the manufacturer to double the memory density on the circuit board. However, the stacking of integrated circuits results in twice as much heat generation as with single layers of integrated circuits, with no corresponding increase in surface area. Consequently, memory modules using stacked integrated circuits have substantial disadvantages over memory modules using a single layer of integrated circuits. Operating at higher temperatures increases the incidence of bit failure. Greater cooling capacity is needed to avoid the problems of high temperature operation. Thermal fatigue and physical failure of the connections between the circuit board and the integrated circuit can result from ongoing heating and cooling cycles.

SUMMARY OF THE INVENTION

A first aspect of the present invention is a memory module comprising a printed circuit board and a plurality of identical integrated circuits. The integrated circuits are mounted on one or both sides of the printed circuit board in first and second rows. The integrated circuits in the first row on a side are oriented in an opposite orientation from the integrated circuits in the second row on the same side. The orientation of the integrated circuits are indicated by an orientation indicia contained on each integrated circuit.

Another aspect of the present invention is a memory module comprising a printed circuit board. A plurality of identical integrated circuits are mounted in two rows on at least one side of the printed circuit board. The memory module also includes a control logic bus, a first register and a second register. The control logic bus is connected to the integrated circuits. The first register and the second register are connected to the control logic bus. Each row of integrated circuits is divided into a first lateral half and a second lateral half. The first register addresses the integrated circuits in the first lateral half of both rows. The second register addresses the integrated circuits in the second lateral half of both rows.

Another aspect of the present invention is a memory module comprising a printed circuit board. A plurality of identical integrated circuits are mounted in two rows on at least one side of the printed circuit board. The memory module includes a control logic bus, a first register and a second register. The control logic bus is connected to the integrated circuits. The first register and the second register are connected to the control logic bus. The first register accesses a first range of data bits and a second range of data bits. The second register accesses a third range of data bits and a fourth range of data bits. The first range of data bits and the second range of data bits are non-contiguous subsets of a data word. The third range of data bits and the fourth range of data bits are also non-contiguous subsets of a data word.

A further aspect of the present invention is a method for arranging integrated circuit locations on a printed circuit board. The method comprises placing locations for the integrated circuits in a first row and a second row onto at least one surface of a printed circuit board. The integrated circuit locations in the second row are oriented 180 degrees relative to an orientation of the integrated circuit locations in the first row.

Another aspect of the present invention is a method for the manufacture of memory modules. The method comprises placing the locations for the integrated circuits on a printed circuit board in a first row and a second row on at least one side of the printed circuit board, and orienting the integrated circuit locations in the first row 180 degrees relative to the orientation of the integrated circuits in the second row. The method further comprises interconnecting the integrated circuit locations in a first half of the first row of integrated circuits and the first half of the second row of integrated circuits to a first register location, and interconnecting the integrated circuit locations in a second half of the first row of integrated circuit locations and the second half of the second row of integrated circuit locations to a second register location. The method also comprises placing identical integrated circuits at the integrated circuit locations in the printed circuit board.

Another aspect of the present invention is a 1-Gigabyte capacity memory module comprising 36 integrated circuits. The integrated circuits are 256-Megabit (i.e., 268,435,456 bits) SDRAM organized as 64 Meg by 4 bits (i.e., 67,108,864 addressed locations with 4 bits per location). The integrated circuits are in a Thin Small Outline Package (TSOP). The memory module has an approximate width of 5.25 inches (133.350 mm) and an approximate height of 2.05 inches (52.073 mm).

Another aspect of the present invention is a 2-Gigabyte capacity memory module comprises 36 integrated circuits. The integrated circuits are 512-Megabit (i.e., 536,870,912 bits) SDRAM organized as 128 Meg by 4 bits (i.e., 134,217,728 addressed locations with 4 bits per location). The integrated circuits are in a Thin Small Outline Package (TSOP). The memory module has an approximate width of 5.25 inches (133.350 mm) and an approximate height of 2.05 inches (52.073 mm).

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the invention.

FIG. 1A illustrates a view of the primary side of a memory module in an embodiment of a PC133 SDRAM memory module

FIG. 1B illustrates a view of the secondary side of the memory module of FIG. 1A.

FIG. 2A illustrates a view of the primary side of a memory module in an embodiment of a DDR SDRAM memory module.

FIG. 2B illustrates a view of the secondary side of the memory module of FIG. 2A.

FIG. 3A is a block diagram of an embodiment of a PC 133 SDRAM memory module.

FIG. 3B is an enlargement of one half of the block diagram of FIG. 3A

FIG. 4A illustrates a portion of the primary signal layer of a printed circuit board in an embodiment of a memory module.

FIG. 4B illustrates a portion of the MID1 layer of a printed circuit board in an embodiment of a memory module.

FIG. 4C illustrates a portion of the MID2 layer of a printed circuit board in an embodiment of a memory module.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In the following description, reference is made to the accompanying drawings, which show, by way of illustration, specific embodiments in which the invention may be practiced. Numemus specific details of these embodiments are set forth in order to provide a thorough understanding of the invention. However, it will be obvious to one skilled in the art that the invention may be practiced without the specific details or with certain alternative components and methods to those described herein.

FIG. 1A illustrates the primary side of an embodiment of a memory module 100. The module 100 comprises two rows of memory integrated circuits 102 mounted onto a printed circuit board 104. The memory module 100 meets the timing standards for and is compatible with JEDEC requirements for a PC133 SDRAM module, but departs from the design guidelines contained in the PC133 design specification. In particular, the memory module 100 meets the timing and interface requirements of the PC133 standard notwithstanding the module 100 having a height (H) of approximately two inches. This height exceeds the 1.75" height guideline recommended in the PC133 Design Specification, but allows a single layer of conventional TSOP integrated circuits 102 to be placed in two rows on each side of the printed circuit board 104, thus avoiding the negative characteristics caused by stacking of integrated circuits and also avoiding the use of more expensive micro-BGA integrated circuits. The printed circuit board maintains a width (W) of 5.25" as defined in the PC133 Design Specification.

The memory module 100 is compatible with the timing requirements while using a greater printed circuit board height through the unique layout and arrangement of the integrated circuits 102 on the printed circuit board and the arrangement of integrated circuit interconnections. As illustrated in FIG. 1A, the upper row of integrated circuits 102 (designated U1 through U10) are oriented in the opposite direction from the lower row of integrated circuits 102 (designated U11 through U18). FIG. 1B illustrates the second side of the embodiment of a memory module 100. The upper row of integrated circuits 102 (designated U24 through U33) on the second side of the printed circuit board 104 are placed in an orientation opposite that of the lower row of integrated circuits 102 (designated U34 through U41). The orientation of each integrated circuit 102 can be advantageously determined from an orientation indicia 106. For example in the illustrated embodiment, the orientation indicia is a small circular mark 106 on the surface of the integrated circuit 102.

The different orientations of the upper row of integrated circuits 102 and the lower row of integrated circuits 102 allow the traces on the signal layer of the memory module 100 to be placed such that the trace lengths to the data pins on the integrated circuits 102 in the first (upper) row have substantially the same length as the signal traces to the data pins on the integrated circuits 102 in the second (lower) row.

FIG. 4A illustrates a portion of a primary signal layer 400 of the printed circuit board 104 of the embodiment of a memory module 100 illustrated in FIGS. 1A and 1B. FIG. 4B illustrates a portion of a MID1 signal layer 430 of the printed circuit board 104 of the embodiment of a memory module illustrated in FIGS. 1A and 1B. FIG. 4C illustrates a portion of a MID2 signal layer 460 of the embodiment of a memory module illustrated in FIGS. 1A and 1B.

The illustrated portion of the primary signal layer 400 connects to the integrated circuits 102 designated U1 and U11. A signal trace 404 to one of the data pins of the U1 integrated circuit is designed to have substantially the same length from the data pin of the U1 integrated circuit to the primary memory module connector 420 as the length of a signal trace 414 from the corresponding data pin in the U11 integrated circuit to the primary memory module connector 420. The signal trace 404 from the U1 integrated circuit to the primary memory module connector 420 and the signal trace 414 from the U11 integrated circuit to the primary memory module connector 420 each include a respective portion of signal trace located on the MID2 layer 460 of the printed circuit board 104, as illustrated in FIG. 4C. Similarly, a signal trace 408 from a second data pin on the U1 integrated circuit to the primary memory module connector 420 is designed to be of substantially the same length as the length of a signal trace 418 from the corresponding pin on the U11 integrated circuit to the primary memory module connector 420. As illustrated in FIG. 4C, the signal traces 408, 418 also include respective portions of the traces located on the MID2 layer 460 of the printed circuit board 104.

A signal trace 402 and a signal trace 406 from third and fourth data pins on the U1 integrated circuit to the primary memory module connector 420 are designed to be substantially the same lengths as the lengths of a signal trace 412 and a signal trace 416 from the corresponding data pins on the U11 integrated circuit to the primary memory module connector 420. As illustrated in FIG. 4B, the signal traces 402, 406, 412, 416 include a portion of the signal trace located on the MID1 layer 430 of the printed circuit board 104.

As shown in FIG. 1A, four signal traces 404, 408, 416, 418 include respective resistors 107 affixed to a first set of connection points 407 (FIG. 4A) on the primary signal layer 400 of the printed circuit board 104. As further shown in FIG. 1A, the four signal traces 402, 406, 418, 414 include respective resistors 109 (FIG. 4A) affixed to a second set of connection points 409 on the primary signal layer 400 of the printed circuit board 104. The resistors 107, 109 complete the circuit paths from the integrated circuit pins to the connector 420 and also provide impedance matching required in the JEDEC standards.

The substantially equal signal trace lengths are repeated for each pair of integrated circuit locations in the first and the second row. By reversing the orientation of the integrated circuits 102 from the first row to the second row, the portions of the signal traces on the primary signal layer 400 serving an integrated circuit in the first row have substantially the same lengths as the signal traces servi