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Multiprocessor node controller circuit and method    
United States Patent6751698   
Link to this pagehttp://www.wikipatents.com/6751698.html
Inventor(s)Deneroff; Martin M. (Palo Alto, CA); Kaldani; Givargis G. (San Jose, CA); Koren; Yuval (San Francisco, CA); McCracken; David Edward (San Francisco, CA); Venkataraman; Swami (San Jose, CA)
AbstractImproved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip. Optionally, the memory is packaged on plugable memory/directory cards wherein each card includes a plurality of memory chips including a first subset dedicated to holding memory data and a second subset dedicated to holding directory data. Further, the memory port includes a memory data port including a memory data bus and a memory address bus coupled to the first subset of memory chips, and a directory data port including a directory data bus and a directory address bus coupled to the second subset of memory chips. In some such embodiments, the ratio of (memory data space) to (directory data space) on each card is set to a value that is based on a size of the multiprocessor computer system.
   














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Multiprocessor node controller circuit and method - US Patent 6751698 Drawing
Multiprocessor node controller circuit and method
Inventor     Deneroff; Martin M. (Palo Alto, CA); Kaldani; Givargis G. (San Jose, CA); Koren; Yuval (San Francisco, CA); McCracken; David Edward (San Francisco, CA); Venkataraman; Swami (San Jose, CA)
Owner/Assignee     Silicon Graphics, Inc. (Mountain View, CA)
Patent assignment
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Publication Date     June 15, 2004
Application Number     09/407,428
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     September 29, 1999
US Classification     710/317
Int'l Classification     G06F 013/00
Examiner     Thai; Xuan M.
Assistant Examiner    
Attorney/Law Firm     Schwegman, Lundberg, Woessner & Kluth, P.A.
Address
Parent Case     CROSS-REFERENCES TO RELATED INVENTIONS This invention is related to application Ser. No. 09/408,874, filed Sep. 29, 1999, entitled "MODULAR COMPUTING ARCHITECTURE HAVING COMMON COMMUNICATION INTERFACE", application Ser. No. 09/408,084, filed Sep. 29, 1999, entitled "TRANSLATION OF PCI LEVEL INTERRUPTS INTO PACKET BASED MESSAGES FOR EDGE EVENT DRIVE MICROPROCESSORS", application Ser. No. 09/522,695, filed Mar. 10, 2000, entitled "SYSTEM AND METHOD FOR A HIERARCHICAL SYSTEM MANAGEMENT ARCHITECTURE OF A HIGHLY SCALABLE COMPUTING SYSTEM", which is a continuation of application Ser. No. 09/407,429, filed Sep. 29, 1999, entitled "HIERARCHICAL SYSTEM MANAGEMENT ARCHITECTURE FOR A HIGHLY SCALABLE COMPUTING SYSTEM", U.S. Pat. No. 6,516,372, issued Feb. 4, 2003, entitled "PARTITIONING A DISTRIBUTED SHARED MEMORY MULTIPROCESSOR COMPUTER TO FACILITATE SELECTIVE HARDWARE MAINTENANCE", application Ser. No. 09/408,972, filed Sep. 29, 1999, entitled "NETWORK TOPOLOGY FOR A SCALABLE MULTIPROCESSOR SYSTEM", application Ser. No. 09/407,421, filed Sep. 29, 1999, entitled "TRANSFER ATTRIBUTE ENCODING WITHIN AN ADDRESS ON A BUS", application Ser. No. 09/408,778, filed Sep. 29, 1999, entitled "AGE-BASED NETWORK ARBITRATION SYSTEM AND METHOD", U.S. Pat. No. 6,085,303, issued Jul. 4, 2000, entitled "SERIALIZED, RACE-FREE VIRTUAL BARRIER NETWORK", U.S. Pat. No. 6,230,252, issued May 8, 2001, entitled "HYBRID HYPERCUBE/TORUS ARCHITECTURE", U.S. Pat. No. 5,970,232, issued Oct. 19, 1999, entitled "ROUTER TABLE LOOKUP MECHANISM", application Ser. No. 08/971,184 filed Nov. 17, 1997 entitled "MULTI-DIMENSIONAL CACHE COHERENCE DIRECTORY STRUCTURE", and U.S. Pat. No. 6,101,181, issued Aug. 8, 2000, entitled "VIRTUAL CHANNEL ASSIGNMENT IN LARGE TORUS SYSTEMS" all of the above of which are hereby incorporated by reference.
Priority Data    
USPTO Field of Search     710/100 710/305 710/306 710/311 710/316 710/317 709/238 709/218 709/249 712/12 370/351 370/419
Patent Tags     multiprocessor node controller circuit
   
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