Local control of multiple context processing elements with configuration contexts

Claims

What is claimed is:

1. A method for locally controlling a first multiple context processing element (MCPE) of a plurality of MCPEs, the first MCPE having network ports connecting the plurality of MCPEs to the first MCPE, the first MCPE being configured to store one or more contexts, the method comprising:

manipulating a context of the first MCPE in response to control information and configuration information,

wherein the plurality of contexts include a plurality of major contexts of configuration memory describing the operation of the first MCPE and wherein at least one of the plurality of major contexts of configuration memory includes at least one minor context.

2. The method of claim 1, wherein manipulating the context further comprises selecting a context to control the function of the first MCPE.

3. The method of claim 1, wherein manipulating the context further comprises programming the first MCPE with a configuration memory context.

4. The method of claim 3, wherein programming the first MCPE is performed simultaneously with the execution of a present function by the first MCPE.

5. The method of claim 1, wherein the first MCPE receives the control information from at least one MCPE and wherein the control information comprises state information.

6. The method of claim 1, wherein the first MCPE receives the control information from a memory of at least one MCPE.

7. The method of claim 1, wherein the the control information comprises maintained data.

8. The method of claim 7, wherein the maintained data comprises a current configuration state of the first MCPE.

9. The method of claim 8, further comprising feeding the current configuration state of the first MCPE back to the first MCPE through a feedback path.

10. The method of claim 1, wherein manipulating one of the plurality of contexts is performed locally at the first MCPE.

11. The method of claim 1, wherein the first MCPE receives the control information from at least one MCPE.

12. The method of claim 1, wherein the first MCPE receives the control information from a MCPE adjacent to the first MCPE.

13. The method of claim 1, wherein the first MCPE receives the control information from an external memory.

14. The method of claim 1, wherein the first MCPE receives at least one bit over a multiple level network from at least one MCPE, the at least one bit representative of at least one configuration context of the at least one MCPE.

15. The method of claim 1, further comprising the first MCPE providing the control information to at least one MCPE of the plurality of MCPEs, the control information for manipulating the context.

16. The method of claim 1, wherein the configuration information comprises data of a current configuration of the first MCPE.

17. The method of claim 1, wherein the configuration information comprises data of a previous configuration of the first MCPE.

18. The method of claim 1, wherein the configuration information comprises state information of the first MCPE.

19. The method of claim 1, wherein the configuration information comprises a signal received commonly by a plurality of MCPEs.

20. The method of claim 1, wherein one or more major contexts contain data describing local network switching.

21. The method of claim 1, wherein each major context of configuration memory includes a plurality of minor contexts.

22. The method of claim 21, wherein the plurality of minor contexts comprise contexts of configurations of network ports of the first MCPE.

23. The method of claim 21, wherein one of the minor contexts is independently writable.

24. The method of claim 21, wherein one of the minor contexts comprises a clear mode.

25. The method of claim 21, wherein one of the minor contexts comprises a freeze mode.

26. The method of claim 21, wherein one of the minor contexts comprises a user-defined operation.

27. The method of claim 1, wherein one of the major contexts is programmable.

28. The method of claim 27, wherein the programmable major context is for user-defined operations.

29. The method of claim 1, wherein one of the major contexts is hardwired.

30. The method of claim 29, wherein the hardwired major context comprises a reset state.

31. The method of claim 29, wherein the hardwired major context comprises a local stall mode.

32. The method of claim 1, further comprising:

assigning a virtual identification (VID) to the first MCPE;

transmitting data comprising an address mask to the first MCPE;

comparing the VID masked with the address mask to a masked destination identification; and

selecting one of the plurality of contexts in response to the transmitted data when the masked VID matches the masked destination identification.

33. The method of claim 1, further comprising programming the first MCPE with data of the plurality of contexts during the execution of a present function by the first MCPE.

34. The method of claim 1, wherein manipulating one of the plurality of contexts is performed during execution of a second context in the first MCPE.

35. In a first multiple context processing element (MCPE) in a network of a plurality of MCPEs, the first MCPE having network ports that connect the plurality of MCPEs to the first MCPE, comprising:

a memory configured to store a plurality of contexts, wherein the plurality of contexts include a plurality of major contexts of configuration memory describing the operation of the first MCPE and wherein at least one of the plurality of major contexts of configuration memory includes at least one minor context; and

a controller coupled to the memory wherein the controller is configured to manipulate one of the plurality of contexts in response to control information and configuration information.

36. The MCPE of claim 35, wherein the controller manipulates one of the contexts by selecting a context to control the function of the first MCPE.

37. The MCPE of claim 35, wherein the controller manipulates one of the contexts by programming the first MCPE with a configuration memory context.

38. The MCPE of claim 37, wherein the controller programs the first MCPE simultaneously with the first MCPE executing a present function.

39. The MCPE of claim 35, wherein the control information comprises state information from at least one MCPE.

40. The MCPE of claim 35, wherein the control information comprises information from a memory of at least one MCPE.

41. The MCPE of claim 35, wherein the control information comprises maintained data.

42. The MCPE of claim 41, wherein the maintained data comprises a current configuration state of the first MCPE.

43. The MCPE of claim 42, further comprising a feedback path to the first MCPE, wherein the current configuration state is provided to the first MCPE through the feedback path.

44. The MCPE of claim 35, wherein the controller manipulates one of the plurality of contexts locally at the first MCPE.

45. The MCPE of claim 35, wherein the first MCPE receives the control information from at least one MCPE.

46. The MCPE of claim 35, wherein the first MCPE receives the control information from a MCPE adjacent to the first MCPE.

47. The MCPE of claim 35, wherein the first MCPE receives the control information from an external memory.

48. The MCPE of claim 35, wherein the first MCPE receives at least one bit received over a multiple level network from at least one MCPE, the at least one bit representative of at least one configuration context of the at least one MCPE.

49. The MCPE of claim 35, wherein the first MCPE provides the control information to at least one MCPE of the plurality of MCPEs, and wherein the controller utilizes the control information to manipulate the context.

50. The MCPE of claim 35, wherein the configuration information comprises data of a current configuration of the first MCPE.

51. The MCPE of claim 35, wherein the configuration information comprises data of a previous configuration of the first MCPE.

52. The MCPE of claim 35, wherein the configuration information comprises state information of the first MCPE.

53. The MCPE of claim 35, wherein the configuration information comprises a signal received commonly by at least some of the plurality of MCPEs.

54. The MCPE of claim 35, wherein one or more major contexts contain data describing local network switching.

55. The MCPE of claim 35, wherein each major context of configuration memory includes a plurality of minor contexts.

56. The MCPE of claim 55, wherein the plurality of minor contexts comprise contexts of configurations of network ports of the first MCPE.

57. The MCPE of claim 55, wherein one of the minor contexts is independently writable.

58. The MCPE of claim 55, wherein one of the minor contexts comprises a clear mode.

59. The MCPE of claim 55, wherein one of the minor contexts comprises a freeze mode.

60. The MCPE of claim 55, wherein one of the minor contexts comprises a user-defined operation.

61. The MCPE of claim 35, wherein one of the major contexts is programmable.

62. The MCPE of claim 61, wherein the programmable major context is for user-defined operations.

63. The MCPE of claim 35, wherein one of the major contexts is hardwired.

64. The MCPE of claim 63, wherein the hardwired major context comprises a reset state.

65. The MCPE of claim 63, wherein the hardwired major context comprises a local stall mode.

66. The MCPE of claim 35, wherein

a virtual identification (VID) is assigned to the first MCPE;

data comprising an address mask is transmitted to the first MCPE

the VID masked with the address mask is compared to a masked destination identification; and

the controller selects one of the plurality of contexts in response to the transmitted data when the masked VID matches the masked destination identification.

FIELD OF THE INVENTION

This invention relates to array based computing devices. More particularly, this invention relates to a semiconductor chip architecture that provides for local control of field programmable gate arrays in a network configuration.

BACKGROUND OF THE INVENTION

Advances in semiconductor technology have greatly increased the processing power of a single chip general purpose computing device. The relatively slow increase in the inter-chip communication bandwidth requires modern high performance devices to use as much of the potential on chip processing power as possible. This results in large, dense integrated circuit devices and a large design space of processing architectures. This design space is generally viewed in terms of granularity, wherein granularity dictates that designers have the option of building very large processing units, or many smaller ones, in the same silicon area. Traditional architectures are either very coarse grain, like microprocessors, or very fine grain, like field programmable gate arrays (FPGAs).

Microprocessors, as coarse grain architecture devices, incorporate a few large processing units that operate on wide data words, each unit being hardwired to perform a defined set of instructions on these data words. Generally, each unit is optimized for a different set of instructions, such as integer and floating point, and the units are generally hardwired to operate in parallel. The hardwired nature of these units allows for very rapid instruction execution. In fact, a great deal of area on modern microprocessor chips is dedicated to cache memories in order to support a very high rate of instruction issue. Thus, the devices efficiently handle very dynamic instruction streams.

Most of the silicon area of modern microprocessors is dedicated to storing data and instructions and to control circuitry. Therefore, most of the silicon area is dedicated to allowing computational tasks to heavily reuse the small active portion of the silicon, the arithmetic logic units (ALUs). Consequently very little of the capacity inherent in a processor gets applied to the problem; most of the capacity goes into supporting a high diversity of operations.

Field programmable gate arrays, as very fine grain devices, incorporate a large number of very small processing elements. These elements are arranged in a configurable interconnected network. The configuration data used to define the functionality of the processing units and the network can be thought of as a very large semantically powerful instruction word allowing nearly any operation to be described and mapped to hardware.

Conventional FPGAs allow finer granularity control over processor operations, and dedicate a minimal area to instruction distribution. Consequently, they can deliver more computations per unit of silicon than processors, on a wide range of operations. However, the lack of resources for instruction distribution in a network of prior art conventional FPGAs make them efficient only when the functional diversity is low, that is when the same operation is required repeatedly and that entire operation can be fit spatially onto the FPGAs in the system.

Furthermore, in prior art FPGA networks, retiming of data is often required in order to delay data. This delay is required because data that is produced by one processing element during one clock cycle may not be required by another processing element until several clock cycles after the clock cycle in which it was made available. One prior art technique for dealing with this problem is to configure some processing elements to function as memory devices to store this data. Another prior art technique configures processing elements as delay registers to be used in the FPGA network. The problem with both of these prior art technique is that valuable silicon is wasted by using processing elements as memory and delay registers.

Dynamically programmable gate arrays (DPGAs) dedicate a modest amount of on-chip area to store additional instructions allowing them to support higher operational diversity than traditional FPGAs. However, the silicon area necessary to support this diversity must be dedicated at fabrication time and consumes area whether or not the additional diversity is required. The amount of diversity supported, that is, the number of instructions supported, is also fixed at fabrication time. Furthermore, when regular data path operations are required all instruction stores are required to be programmed with the same data using a global signal broadcasted to all DPGAs.

The limitations present in the prior art FPGA and DPGA networks in the form of limited control over configuration of the individual FPGAs and DPGAs of the network severely limits the functional diversity of the networks. For example, in one prior art FPGA network, all FPGAs must be configured at the same time to contain the same configurations. Consequently, rather than separate the resources for instruction storage and distribution from the resources for data storage and computation, and dedicate silicon resources to each of these resources at fabrication time, there is a need for an architecture that unifies these resources. Once unified, traditional instruction and control resources can be decomposed along with computing resources and can be deployed in an application specific manner. Chip capacity can be selectively deployed to dynamically support active computation or control reuse of computational resources depending on the needs of the application and the available hardware resources.

SUMMARY OF THE INVENTION

A method and apparatus for providing local control of processing elements in a network of multiple context processing element are provided. According to one aspect of the invention, a multiple context processing element is configured to store a number of configuration memory contexts. This multiple context processing element maintains data of a current configuration. State information is received from at least one other multiple context processing element. The state information comprises at least one bit received over a multiple level network, the bit representative of at least one configuration memory context of the multiple context processing element from which it is received. At least one configuration control signal is generated in response to the state information and the data of a current configuration. One of multiple configuration memory contexts is selected in response to the received state information and the data of a current configuration. The selected configuration memory context controls the multiple context processing element.

Each multiple context processing element in the networked array of multiple context processing elements has an assigned physical and virtual identification. Data is transmitted to at least one of the multiple context processing elements of the array, the data comprising control data, configuration data, an address mask, and a destination identification. The transmitted address mask is applied to either the physical or virtual identification and to a destination identification. The masked physical or virtual identification is compared to the masked destination identification. When the masked physical or virtual identification of a multiple context processing element matches the masked destination identification, at least one of the number of multiple context processing elements are manipulated in response to the transmitted data. Manipulation comprises selecting one of a number of configuration memory contexts to control the functioning of the multiple context processing element.

These and other features, aspects, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description and appended claims which follow.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which