System and method for self-testing and repair of memory modules

Claims

What is claimed is:

1. A memory module, comprising:

a plurality of memory devices; and

a memory hub, comprising:

a self-test module coupled to at least one of the memory devices, the self-test module being responsive to a request to test at least one of the memory devices, the self-test module further being operable to identify defective memory locations of the memory devices; and

a repair module coupled to the self-test module and at least one of the memory devices, the repair module being responsive to memory requests to defective memory locations of the memory devices to redirect the memory requests to non-defective memory locations of the memory devices.

2. The memory module of claim 1 wherein the self-test module further comprises a sequencer for accessing the memory devices, the sequencer being operable to output an address, contained in memory requests from the self-test module, for accessing memory locations of the memory devices.

3. The memory module of claim 1 wherein the memory module further comprises:

a link interface for receiving memory requests to at least one of the memory devices;

a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices; and

a memory controller coupled to the link interface and the memory device interface and the repair module, the memory controller being operable to generate and couple memory requests from the link interface to the memory device interface by utilizing the repair module to redirect memory requests to defective locations of the memory devices to non-defective locations of the memory devices.

4. The memory module of claim 3 wherein the memory controller further comprises a sequencer for accessing the memory devices, the sequencer being operable to output an address, contained in memory requests from the self-test routines, for accessing memory locations of the memory devices.

5. The memory module of claim 3 wherein the memory device interface further comprises a first-in, first-out buffer that is operable to receive and to store memory requests received from the memory controller and to transfer the stored memory requests to at least one of the memory devices in the order in which they were received.

6. The memory module of claim 3 wherein the link interface comprises a first-in, first-out buffer that is operable to receive and store memory requests and to transfer the stored memory requests to the memory controller in the order in which they were received.

7. The memory module of claim 1 wherein information identifying the defective memory locations of the memory devices is transferred from the self-test module to the repair module.

8. The memory module of claim 1 wherein the self-test module is coupled to at least one of the memory access devices, the locations of the defective memory of the memory devices being transferred to at least one of the memory access device.

9. The memory module of claim 1 wherein the repair module further comprises an error map that stores the locations of the defective memory of the memory devices, the repair module utilizing the error map to determine whether the memory requests are to defective memory locations of the memory devices.

10. The memory module of claim 9 wherein the repair module further comprises a remapping table that uses the error map to assign the defective memory locations of the memory devices to non-defective memory locations of memory located on the memory module, the repair module using the remapping table to redirect memory requests to defective memory locations of the memory devices to non-defective memory locations of the memory devices.

11. The memory module of claim 1 wherein the memory devices comprise dynamic random access memory devices.

12. A memory module, comprising:

a plurality of memory devices; and

a memory hub, comprising:

a memory controller coupled to at least one of the memory devices, the memory controller being responsive to memory requests to the memory devices;

a self-test module coupled to the memory controller, the self-test module being responsive to a request to test at least one of the memory devices, the self-test module further being operable to identify defective memory locations of the memory devices; and

a repair module coupled to the memory controller, the repair module being responsive to memory requests to defective memory locations of the memory devices to redirect the memory requests to non-defective memory locations of the memory devices.

13. The memory module of claim 12 wherein the memory controller further comprises a sequencer for accessing the memory devices, the sequencer being operable to output an address, contained in memory requests from the self-test module, for accessing memory locations of the memory devices.

14. The memory module of claim 12 wherein the memory module further comprises:

a link interface coupled to the memory controller for receiving memory requests to at least one of the memory devices; and

a memory device interface coupled to the memory controller and the memory devices, the memory device interface being operable to couple memory requests to the memory devices.

15. The memory module of claim 14 wherein the memory controller generates and couples memory requests from the link interface to the memory device interface by utilizing the repair module to redirect memory requests to defective locations of the memory devices to non-defective locations of the memory devices.

16. The memory module of claim 14 wherein the memory device interface further comprises a first-in, first-out buffer that is operable to receive and to store memory requests received from the memory controller and to transfer the stored memory requests to at least one of the memory devices in the order in which they were received.

17. The memory module of claim 14 wherein the link interface comprises a first-in, first-out buffer that is operable to receive and store memory requests and to transfer the stored memory requests to the memory controller in the order in which they were received.

18. The memory module of claim 12 wherein information identifying the defective memory locations of the memory devices is transferred from the self-test module to the repair module.

19. The memory module of claim 12 wherein the self-test module is coupled to at least one of the memory access devices, the locations of the defective memory of the memory devices being transferred to at least one of the memory access devices.

20. The memory module of claim 12 wherein the repair module further comprises an error map that stores the locations of the defective memory of the memory devices, the repair module utilizing the error map to determine whether the memory requests are to defective memory locations of the memory devices.

21. The memory module of claim 20 wherein the repair module further comprises a remapping table that uses the error map to assign the defective memory locations of the memory devices to non-defective memory locations of memory located on the memory module, the repair module using the remapping table to redirect memory requests to defective memory locations of the memory devices to non-defective memory locations of the memory devices.

22. The memory module of claim 21 wherein the memory controller further comprises the error map of the repair module, the error map being operable to determine whether the memory request is to a defective memory location of the memory devices.

23. The memory module of claim 22 wherein the memory controller further comprises the remapping table of the repair module, the remapping table being operable to redirect the memory requests to defective locations of the memory devices to non-defective locations of the memory devices.

24. The memory module of claim 12 wherein the memory devices comprise dynamic random access memory devices.

25. A computer system, comprising:

a central processing unit ("CPU");

a system controller coupled to the CPU, the system controller having an input port and an output port;

an input device coupled to the CPU through the system controller;

an output device coupled to the CPU through the system controller;

a storage device coupled to the CPU through the system controller;

a plurality of memory modules, each of the memory modules comprising:

a plurality of memory devices; and

a memory hub, comprising:

a self-test module coupled to at least one of the memory devices, the self-test module being responsive to a request to test at least one of the memory devices, the self-test module further being operable to identify defective memory locations of the memory devices;

a repair module coupled to the self-test module and at least one of the memory devices, the repair module being responsive to memory requests to defective memory locations of the memory devices to redirect the memory requests to non-defective memory locations of the memory devices; and

a communications link coupling the output port of the system controller to the input port of the memory hub in each of the memory modules, and coupling the input port of the system controller to the output port of the memory hub in each of the memory modules.

26. The computer system of claim 25 wherein the self-test module further comprises a sequencer for accessing the memory devices, the sequencer being operable to output an address, contained in memory requests from the self-test module, for accessing memory locations of the memory devices.

27. The computer system of claim 25 wherein the memory module further comprises:

a link interface for receiving memory requests to at least one of the memory devices;

a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices; and

a memory controller coupled to the link interface and the memory device interface and the repair module, the memory controller being operable to generate and couple memory requests from the link interface to the memory device interface by utilizing the repair module to redirect memory requests to defective locations of the memory devices to non-defective locations of the memory devices.

28. The computer system of claim 27 wherein the memory controller further comprises a sequencer for accessing the memory devices, the sequencer being operable to output an address, contained in memory requests from the self-test routines, for accessing memory locations of the memory devices.

29. The computer system of claim 27 wherein the memory device interface further comprises a first-in, first-out buffer that is operable to receive and to store memory requests received from the memory controller and to transfer the stored memory requests to at least one of the memory devices in the order in which they were received.

30. The computer system of claim 27 wherein the link interface comprises a first-in, first-out buffer that is operable to receive and store memory requests and to transfer the stored memory requests to the memory controller in the order in which they were received.

31. The computer system of claim 25 wherein information identifying the defective memory locations of the memory devices is transferred from the self-test module to the repair module.

32. The computer system of claim 25 wherein the self-test module is coupled to at least one of the memory access devices, the locations of the defective memory of the memory devices being transferred to at least one of the memory access device.

33. The computer system of claim 25 wherein the repair module further comprises an error map that stores the locations of the defective memory of the memory devices, the repair module utilizing the error map to determine whether the memory requests are to defective memory locations of the memory devices.

34. The computer system of claim 33 wherein the repair module further comprises a remapping table that uses the error map to assign the defective memory locations of the memory devices to non-defective memory locations of memory located on the memory module, the repair module using the remapping table to redirect memory requests to defective memory locations of the memory devices to non-defective memory locations of the memory devices.

35. The computer system of claim 25 wherein the memory devices comprise dynamic random access memory devices.

36. The computer system of claim 25 wherein the input and output ports of the memory hub controller comprise a combined input/output port coupled to the communications link, and wherein the input and output ports of each of the memory hubs comprises a combined input/output port coupled to the communications link.

37. The computer system of claim 36 wherein the communications link comprises an optical communications link, wherein the input and output ports of the memory hub controller comprises an optical input/output port coupled to the optical communications link and wherein the input and output ports of each of the memory hubs comprises a respective optical input/output port coupled to the optical communications link.

38. A computer system, comprising:

a central processing unit ("CPU");

a system controller coupled to the CPU, the system controller having an input port and an output port;

an input device coupled to the CPU through the system controller;

an output device coupled to the CPU through the system controller;

a storage device coupled to the CPU through the system controller;

a plurality of memory modules, each of the memory modules comprising:

a plurality of memory devices; and

a memory hub, comprising:

a memory controller coupled to at least one of the memory devices, the memory controller being responsive to memory requests to the memory devices;

a self-test module coupled to the memory controller, the self-test module being responsive to a request to test at least one of the memory devices, the self-test module further being operable to identify defective memory locations of the memory devices; and

a repair module coupled to the memory controller, the repair module being responsive to memory requests to defective memory locations of the memory devices to redirect the memory requests to non-defective memory locations of the memory devices;

a communications link coupling the output port of the system controller to the input port of the memory hub in each of the memory modules, and coupling the input port of the system controller to the output port of the memory hub in each of the memory modules.

39. The computer system of claim 38 wherein the memory controller further comprises a sequencer for accessing the memory devices, the sequencer being operable to output an address, contained in memory requests from the self-test module, for accessing memory locations of the memory devices.

40. The computer system of claim 38 wherein the memory module further comprises:

a link interface coupled to the memory controller for receiving memory requests to at least one of the memory devices; and

a memory device interface coupled to the memory controller and the memory devices, the memory device interface being operable to couple memory requests to the memory devices.

41. The computer system of claim 40 wherein the memory controller generates and couples memory requests from the link interface to the memory device interface by utilizing the repair module to redirect memory requests to defective locations of the memory devices to non-defective locations of the memory devices.

42. The computer system of claim 40 wherein the memory device interface further comprises a first-in, first-out buffer that is operable to receive and to store memory requests received from the memory controller and to transfer the stored memory requests to at least one of the memory devices in the order in which they were received.

43. The computer system of claim 40 wherein the link interface comprises a first-in, first-out buffer that is operable to receive and store memory requests and to transfer the stored memory requests to the memory controller in the order in which they were received.

44. The computer system of claim 38 wherein information identifying the defective memory locations of the memory devices is transferred from the self-test module to the repair module.

45. The computer system of claim 38 wherein the self-test module is coupled to at least one of the memory access devices, the locations of the defective memory of the memory devices being transferred to at least one of the memory access devices.

46. The computer system of claim 38 wherein the repair module further comprises an error map that stores the locations of the defective memory of the memory devices, the repair module utilizing the error map to determine whether the memory requests are to defective memory locations of the memory devices.

47. The computer system of claim 46 wherein the repair module further comprises a remapping table that uses the error map to assign the defective memory locations of the memory devices to non-defective memory locations of memory located on the memory module, the repair module using the remapping table to redirect memory requests to defective memory locations of the memory devices to non-defective memory locations of the memory devices.

48. The computer system of claim 47 wherein the memory controller further comprises the error map of the repair module, the error map being operable to determine whether the memory request is to a defective memory location of the memory devices.

49. The computer system of claim 48 wherein the memory controller further comprises the remapping table of the repair module, the remapping table being operable to redirect the memory requests to defective locations of the memory devices to non-defective locations of the memory devices.

50. The computer system of claim 38 wherein the memory devices comprise dynamic random access memory devices.

51. The computer system of claim 38 wherein the input and output ports of the memory hub controller comprise a combined input/output port coupled to the communications link, and wherein the input and output ports of each of the memory hubs comprises a combined input/output port coupled to the communications link.

52. The computer system of claim 51 wherein the communications link comprises an optical communications link, wherein the input and output ports of the memory hub controller comprises an optical input/output port coupled to the optical communications link and wherein the input and output ports of each of the memory hubs comprises a respective optical input/output port coupled to the optical communications link.

53. A method of testing and repairing each of a plurality of memory devices on each of a plurality of memory modules each of which includes a memory hub, the method comprising:

using the memory hub in at least one of the memory modules to generate a self-test routine;

using a generated self-test routine to test at least one of the memory devices in the memory module to identify defective memory locations of the at least one memory device;

receiving a memory request at the memory hub to access at least one of the memory devices;

determining at the memory hub if the received memory request is directed to a memory location identified as being a defective memory location;

if the received memory request is directed to a memory location identified as being a defective memory location, redirecting the memory request to a non-defective location of memory on the memory module; and

if the received memory request is directed to a memory location that was not identified as being a defective memory location, accessing the location in the at least one memory device to which the memory request was directed.

54. The method of claim 53 and further comprising storing information identifying the defective memory locations of the memory devices in an error map.

55. The method of claim 54, further comprising creating a remapping table from the error map that assigns the defective memory locations of the memory devices to non-defective memory locations of the memory devices, the remapping table being used to redirect the memory requests directed to the defective memory locations of the memory devices to non-defective memory locations of the memory devices.