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Testing of integrated circuit devices    

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United States Patent6754866   
Link to this pagehttp://www.wikipatents.com/6754866.html
Inventor(s)Ong; Adrian E. (Pleasanton, CA); Ho; Fan (San Ramon, CA)
AbstractAn integrated circuit device includes a data buffer, coupled to an external connector, providing a data signal on the external connector. A test buffer, coupled to the data buffer, receives the data signal and provides a testing output signal to a delay circuit. The delay circuit receives the testing output signal at a first clock rate internal to the integrated circuit device and compares test data in the testing output signal to expected test signal values. The delay circuit provides a result to an external connector at a second clock rate that is slower than the first clock rate.
   














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Patent Text Patent PDF Print Page Summary File History
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Inventor     Ong; Adrian E. (Pleasanton, CA); Ho; Fan (San Ramon, CA)
Owner/Assignee     Inapac Technology, Inc. (San Jose, CA)
Patent assignment
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Company News
Publication Date     June 22, 2004
Application Number     09/967,389
PAIR File History     Application Data   Transaction History
Image File Wrapper   Patent Term   Fees
Litigation
Filing Date     September 28, 2001
US Classification     714/736 713/401 714/718 714/819
Int'l Classification     G06F 011/00 G06F 007/02 H04L 007/00
Examiner     Tu; Christine T.
Assistant Examiner    
Attorney/Law Firm     Sidley Austin Brown & Wood LLP
Address
Parent Case     RELATED APPLICATION This application is a related to U.S. patent application Ser. No. 09/666,208 filed Sep. 21, 2000, entitled "CHIP TESTING WITHIN A MULTI-CHIP SEMICONDUCTOR PACKAGE," assigned to the same assignee and incorporated by reference herein.
Priority Data    
USPTO Field of Search     714/736 714/814 714/819 714/738 714/798 714/799 714/724 714/824 714/718 714/719 713/400 713/401 713/500 713/600 324/210 324/211 324/212
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Huisman

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