Semiconductor device, a semiconductor module loaded with said semiconductor device and a method of manufacturing said semiconductor device

What is claimed is:

1. A tape carrier type semiconductor device for mounting plural chips to one tape, wherein common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and said common signal terminals on the two sides are electrically connected to each other by common signal wiring; and wherein pads of said chips are set such that a pad connected to said common signal wiring is arranged far from said independent signal terminal, and a pad connected to independent signal wiring is arranged near said independent signal terminal.

2. A tape carrier type semiconductor device for mounting plural chips to one tape, wherein common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and said common signal terminals on the two sides are electrically connected to each other by common signal wiring; wherein said tape is a two-layer tape; and wherein a ground electric potential plane pattern and a power electric potential plane pattern are formed on a face opposed to a forming face of said common signal wiring and independent signal wiring in said two-layer tape.

3. A tape carrier type semiconductor device for mounting plural chips to one tape, wherein common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and said common signal terminals on the two sides are electrically connected to each other by common signal wiring; wherein said tape is a two-layer tape; and wherein an insulating material is interposed between a main face of said chip and signal wiring of said two-layer tape.

4. A tape carrier type semiconductor device for mounting plural chips to one tape, wherein common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and said common signal terminals on the two sides are electrically connected to each other by common signal wiring; wherein a frame is arranged on one face of said tape so as to surround said chip; and wherein said frame is constructed by plastic or a metal having a good head radiating property.

5. A tape carrier type semiconductor device for mounting plural chips to one tape, wherein common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and said common signal terminals on the two sides are electrically connected to each other by common signal wiring; and wherein a metallic plate is fixedly attached to said chip.

6. A tape carrier type semiconductor device for mounting plural chips to one tape, wherein common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and said common signal terminals on the two sides are electrically connected to each other by common signal wiring; and wherein said independent signal terminal and another independent signal terminal electrically unconnected to the chip mounted to said tape are arranged on said another side.

7. A tape carrier type semiconductor device for mounting plural chips to one tape, wherein common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and the common signal terminals arranged on said one set of two opposed sides are arranged with left-right mirror symmetry; and wherein two mirror symmetry tape carrier type semiconductor devices are formed by cutting said tape along a central line on one side on which said independent signal terminal is arranged.

8. The semiconductor device according to claim 7, wherein a recognizing mark pattern is formed in said tape of each of said two mirror symmetry tape carrier type semiconductor devices.

9. The semiconductor device according to claim 7, wherein an index for pin display is formed in said tape of each of said two mirror symmetry tape carrier type semiconductor devices.

10. A tape carrier type semiconductor device for mounting plural chips to one tape, wherein common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and a lead continuously extends to said common signal terminals and said independent signal terminal and is projected from said tape, and said common signal terminals on the two sides are electrically connected to each other by common signal wiring; and wherein pads of said chips are set such that a pad connected to said common signal wiring is arranged far from said independent signal terminal, and a pad connected to independent signal wiring is arranged near said independent signal terminal.

11. A tape carrier type semiconductor device for mounting plural chips to one tape, wherein common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and a lead continuously extends to said common signal terminals and said independent signal terminal and is projected from said tape, and said common signal terminals on the two sides are electrically connected to each other by common signal wiring; and wherein plural support leads electrically unconnected to the mounted chip are arranged on another side opposed to the lead of said independent signal terminal.

12. A tape carrier type semiconductor device for mounting plural chips to one tape, wherein common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and a lead continuously extends to said common signal terminals and said independent signal terminal and is projected from said tape, and said common signal terminals on the two sides are electrically connected to each other by common signal wiring; wherein a frame is arranged on one face of said tape so as to surround said chip; and wherein said frame is constructed by plastic or a metal having a good heat radiating property.

13. A tape carrier type semiconductor device of a laminating type for mounting plural chips to one tape, wherein a semiconductor device having common signal terminals arranged on one set of two opposed sides, a first independent signal terminal arranged on another side, and a second independent signal terminal electrically unconnected to the chips mounted to said tape is laminated, and the first independent signal terminal at an upper stage and the second independent signal terminal at a lower stage are connected to each other, and the second independent signal terminal at the upper stage and the first independent signal terminal at the lower stage are connected to each other.

14. The semiconductor device of a laminating type according to claim 13, wherein said laminated semiconductor device is laminated by connecting said signal terminals formed on said tape to each other.

15. The semiconductor device of a laminating type according to claim 13, wherein said laminated semiconductor device has a structure in which the signal terminals are formed on the tape at the lower stage, and also has a structure constructed by a lead terminal continuously extending from said signal terminals at the upper stage, and these structures are laminated with each other.

16. The semiconductor device of a laminating type according to claim 13, wherein said laminated semiconductor device has a structure having lead terminals respectively continuously extending from the signal terminals, and is laminated by connecting said lead terminals to each other.

17. The semiconductor device of a laminating type according to claim 13, wherein a recognizing mark pattern is formed in said tape.

18. The semiconductor device of a laminating type according to claim 13, wherein an index for pin display is formed in said tape.

19. A semiconductor module mounting plural tape carrier type semiconductor devices thereto in which plural external terminals are formed on one long side of a rectangular substrate, and common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and said common signal terminals on the two sides are electrically connected to each other by common signal wiring, and plural chips are mounted to one tape, wherein said independent signal terminal is arranged along an arranging direction of said external terminals; and wherein the semiconductor module is constructed by mixing said tape carrier type semiconductor device mounting four chips onto one tape, and a tape carrier type semiconductor device in which common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and the common signal terminals arranged on said one set of two opposed sides are arranged with left-right mirror symmetry, and two chips are mounted onto one tape.

20. A semiconductor module mounting plural tape carrier type semiconductor devices thereto in which plural external terminals are formed on one long side of a rectangular substrate, and common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and a lead continuously extends to said common signal terminals and said independent signal terminal and is projected from a tape, and said common signal terminals on the two sides are electrically connected to each other by common signal wiring, and plural chips are mounted to one tape, wherein said independent signal terminal is arranged along an arranging direction of said external terminals; and wherein the semiconductor module is constructed by mixing said tape carrier type semiconductor device mounting four chips onto one tape, and a tape carrier type semiconductor device in which common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and the common signal terminals arranged on said one set of two opposed sides are arranged with left-right mirror symmetry, and two chips are mounted onto one tape.

21. A semiconductor module constructed by laminating a semiconductor device in which plural external terminals are formed on one long side of a rectangular substrate, and common signal terminals are arranged on one set of two opposed sides, and a first independent signal terminal is arranged on another side, and a second independent signal terminal electrically unconnected to a chip mounted to a tape is arranged; and mounting plural tape carrier type semiconductor devices in which the first independent signal terminal at an upper stage and the second independent signal terminal at a lower stage are connected to each other, and the second independent signal terminal at the upper stage and the first independent signal terminal at the lower stage are connected to each other, and plural chips are mounted to one tape, wherein said independent signal terminal is arranged along an arranging direction of said external terminals.

22. The semiconductor module according to claim 21, wherein each of said plural tape carrier type semiconductor devices is laminated by connecting said signal terminals formed on said tape to each other.

23. The semiconductor module according to claim 21, wherein each of said plural tape carrier type semiconductor devices has a structure in which the signal terminals are formed on the tape at the lower stage, and also has a structure constructed by a lead terminal continuously extending from said signal terminals at the upper stage, and these structures are laminated with each other.

24. The semiconductor module according to claim 21, wherein each of said plural tape carrier type semiconductor devices has a structure having lead terminals respectively continuously extending from the signal terminals, and is laminated by connecting said lead terminals to each other.

25. The semiconductor module of a lead-on-board structure according to claim 21, wherein each of said plural tape carrier type semiconductor devices has a structure having lead terminals respectively continuously extending from the signal terminals, and is laminated onto the mounting substrate such that said lead terminal of the tape carrier type semiconductor device mounted at the upper stage lies across said lead terminal of the tape carrier type semiconductor device mounted at the lower stage.

26. The semiconductor module according to claim 25, wherein a lead of said tape carrier type semiconductor device at the upper stage is longer in said lead-on-board structure.

27. The semiconductor module according to claim 21, wherein a resin seal type semiconductor device is mounted between said external terminals and said plural tape carrier type semiconductor devices.

28. The semiconductor module according to claim 21, wherein the semiconductor module is constructed by mixing said tape carrier type semiconductor device mounting four chips onto one tape, and a tape carrier type semiconductor device in which common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and the common signal terminals arranged on said one set of two opposed sides are arranged with left-right mirror symmetry, and two chips are mounted onto one tape.

29. The semiconductor module according to claim 21, wherein a mounting face of said substrate and a chip main face are mounted such that these faces are facing each other.

30. A tape carrier type semiconductor device for mounting plural chips to one tape, wherein common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and a lead continuously extends to said common signal terminals and said independent signal terminal and is projected from said tape, and said common signal terminals on the two sides are electrically connected to each other by common signal wiring; and wherein a metallic plate is fixedly attached to said chip.

Description Submit all comments and votes

FIELD OF THE INVENTION

The present invention relates to a semiconductor device, a semiconductor module loaded with the semiconductor device, and a manufacturing technique of the semiconductor module, and particularly relates to a tape carrier type semiconductor device (TCP: Tape Carrier Package) for mounting plural chips to one tape, and an effective technique applied to a semiconductor module loaded with plural TCPs.

BACKGROUND OF THE INVENTION

For example, when a memory TCP such as a DRAM is made as a conventional manufacturing technique of the tape carrier package, there is a one-chip built-in TCP package in which a series of insulating tapes forming lead wiring therein is used, and an individual memory chip is sequentially mounted to these insulating tapes, and the memory chip and the lead wiring are finally set to a pair.

In manufacture of this memory TCP, for example, in a selecting process, a material processed in a tape shape so far is conveyed in a state in which this material is cut into an individual piece. For example, it is indispensable in this individual tape piece described in Japanese Patent Laid-Open No. 37141/1994 that a pad for a test probe is arranged around an outer lead. An outer shape size of the individual tape piece is four times or more in area in comparison with a TSOP (Thin Small Outline Package), etc. Accordingly, a socket for burn-in and a test is also four times or more in area in comparison with the TSOP. Further, when the test is terminated, the individual tape piece is cut in an outer lead portion in a final process, and the outer lead is formed in a gull-wing shape, and is stored to a tray.

Further, for example, when this memory TCP is produced as a memory module, the memory TCP is again picked up one by one from the tray, and plural memory TCPs are mounted onto a substrate and are completed as a memory module of a predetermined capacity in a module mounting process.

SUMMARY OF THE INVENTION

With respect to the technique of the memory TCP mentioned above and the memory module loaded with this memory TCP, the following contents have become clear as a result of consideration of the prevent inventors. For example, in manufacture of the memory TCP, the individual tape piece for burn-in and a test is large in size so that a socket size mountable in comparison with the TSOP is increased. Therefore, the number of sockets attached to a board for burn-in and a test is greatly reduced. As a result, a processing number is reduced, in other words, cost is increased.

Further, the material is conveyed in a tape state until a seal process in a TAB (Tape Automated Bonding) process itself. However, after the selecting process, the material is individually cut, and is again mounted to the memory module one by one in the memory module mounting process. This is disadvantageous in view of mounting cost and mounting area. Accordingly, it is considered that an efficient process at low cost is realized if the tape is supplied to the memory module process as it is, and the tape can be simultaneously cut and mounted to the substrate.

As an example of the memory module, for example, there is a memory module described in Japanese Patent Laid-Open No. 350961/1992. In this memory module, lead wiring of the tape is set to multiple layers, and plural chips mounted through an insulating film are electrically connected to each other. In this technique, the lead wiring of the tape and a chip are connected to each other by wire bonding, and it is necessary to draw lead wiring for a common signal common to chips around one side of the module so that a wiring layer is required every common signal. Accordingly, the number of layers in a tape structure is extremely large. Therefore, it is considered that it is difficult to design the tape and it is disadvantageous in cost.

Therefore, an object of the invention is to provide a semiconductor device able to reduce tape cost and burn-in and test cost by simplifying a tape design and increasing a simultaneous processing number in burn-in and test using an assembly process of a TCP, and further provide a semiconductor module able to reduce substrate cost and module mounting cost by mounting plural semiconductor devices and simplifying a substrate design and efficiently performing module mounting.

The above and other objects and novel features of the invention will become apparent from the description and the accompanying drawings of the present specification.

Summaries of typical inventions among the inventions disclosed in the present application will be explained briefly as follows.

Namely, a first semiconductor device in the invention as the structure of a basic multi-chip TCP is a tape carrier type semiconductor device for mounting plural chips to one tape in which common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and the common signal terminals on the two sides are electrically connected to each other by common signal wiring.

A second semiconductor device in the invention as the structure of a multi-chip TCP able to be divided into two portions is a tape carrier type semiconductor device for mounting plural chips to one tape in which common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and the common signal terminals arranged on the one set of two opposed sides are arranged with left-right mirror symmetry. Further, two mirror symmetry tape carrier type semiconductor devices are formed by cutting the tape at its center.

Further, a third semiconductor device in the invention as the structure of a multi-chip TCP of a lead type is a tape carrier type semiconductor device for mounting plural chips to one tape in which common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side, and a lead continuously extends to the common signal terminals and the independent signal terminal and is projected from the tape, and the common signal terminals on the two sides are electrically connected to each other by common signal wiring. Further, plural support leads electrically unconnected to the mounted chip are arranged on another side opposed to the lead of the independent signal terminal.

Further, a fourth semiconductor device in the invention as the structure of a multi-chip TCP able to be laminated is a tape carrier type semiconductor device for mounting plural chips to one tape in which a semiconductor device having common signal terminals arranged on one set of two opposed sides, a first independent signal terminal arranged on another side, and a second independent signal terminal electrically unconnected to the chips mounted to the tape is laminated, and the first independent signal terminal at an upper stage and the second independent signal terminal at a lower stage are connected to each other, and the second independent signal terminal at the upper stage and the first independent signal terminal at the lower stage are connected to each other. Further, the laminated semiconductor device is laminated by a tape-on-tape structure, a lead-on-tape structure or a lead-on-lead structure.

In the structure of each of the first, second, third and fourth semiconductor devices, pads of the chip are set such that a pad connected to the common signal wiring is arranged far from the independent signal terminal, and a pad connected to independent signal wiring is arranged near the independent signal terminal. Further, the common signal wiring and the independent signal wiring formed on the tape are located on the same face, and do not cross each other.

The tape is a one-layer tape or a two-layer tape. A ground electric potential plane pattern and a power electric potential plane pattern are mainly formed on a face opposed to a forming face of the common signal wiring and the independent signal wiring in the two-layer tape. Further, an insulating material is interposed between a main face of the chip and signal wiring of the two-layer tape.

Chip parts are mounted to the tape. A frame is also arranged on one face of the tape so as to surround the chip. The frame is constructed by plastic or a metal having a good heat radiating property. A metallic plate is fixedly attached to the chip.

A recognizing mark pattern is formed in the tape. Further, an index for pin display is formed in the tape.

The independent signal terminal and another independent signal terminal electrically unconnected to the chip mounted to the tape are arranged on the another side.

A first semiconductor module in the invention is a semiconductor module mounting the plural first semiconductor devices thereto in which plural external terminals are formed on one long side of a rectangular substrate, and the independent signal terminal is arranged along an arranging direction of the external terminals. Further, the first semiconductor device loaded with four chips and the second semiconductor device loaded with two chips are mixed with each other.

A second semiconductor module in the invention is a semiconductor module mounting the plural third semiconductor devices thereto in which plural external terminals are formed on one long side of a rectangular substrate, and the independent signal terminal is arranged along an arranging direction of the external terminals. Further, the first semiconductor device loaded with four chips and the second semiconductor device loaded with two chips are mixed with each other.

Further, a third semiconductor module in the invention is a semiconductor module mounting the plural fourth semiconductor devices thereto in which plural external terminals are formed on one long side of a rectangular substrate, and the independent signal terminal is arranged along an arranging direction of the external terminals. Further, the plural semiconductor devices are laminated by the tape-on-tape structure, the lead-on-tape structure, the lead-on-lead structure or a lead-on-board structure. In the lead-on-board structure, the lead of the semiconductor device at the lower stage lies across the lead of the semiconductor device at the upper stage, and the lead of the semiconductor device at the upper stage is longer. Further, the first semiconductor device loaded with four chips and the second semiconductor device loaded with two chips are mixed with each other.

In the structures of the first, second and third semiconductor modules, a resin seal type semiconductor device is mounted between the external terminals and the plural semiconductor devices. Further, a mounting face of the substrate and a chip main face are mounted such that these faces are facing each other.

In a manufacturing method of the semiconductor module in the invention, a tape carrier type semiconductor device loaded with plural chips is completed by cutting a series of tapes forming common signal terminals therein every plural chips approximately along a central line so as to divide these common signal terminals into two portions in a tape cut process of an assembly process of the tape carrier type semiconductor device. Further, the tape carrier type semiconductor device loaded with the plural chips is divided into two portions in a portion in which there are no common signal terminals. When the tape carrier type semiconductor device loaded with the plural chips is completed, the tapes are cut every four chips, and are cut in a unit of two chips in a portion in which there are no common signal terminals.

Accordingly, in accordance with the invention, it is possible to manufacture a first semiconductor device as the structure of a basic multi-chip TCP, a second semiconductor device as the structure of a multi-chip TCP able to be divided into two portions, a third semiconductor device as the structure of a multi-chip TCP of a lead type, and a fourth semiconductor device as the structure of a multi-chip TCP able to be laminated. Further, it is possible to manufacture a first semiconductor module loaded with the first semiconductor device (mixed with the second semiconductor device), a second semiconductor module loaded with the third semiconductor device (mixed with the first and second semiconductor devices), and a third semiconductor module loaded with the fourth semiconductor device (mixed with the first and second semiconductor devices) by combining the first to fourth semiconductor devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the relation of a semiconductor device in one embodiment mode of the invention and a semiconductor module loaded with this semiconductor device.

FIG. 2 is a plan view showing the semiconductor device of this embodiment mode.

FIGS. 3A and 3B are respectively a cross-sectional view and a partially enlarged sectional view showing the semiconductor device of this embodiment mode.

FIGS. 4A and 4B are views of front and rear face patterns showing a two-layer tape in this embodiment mode.

FIG. 5 is a plan view showing a main face of a chip in this embodiment mode.

FIGS. 6A and 6B are respectively a cross-sectional view and a partially enlarged sectional view showing a memory TCP when bonding is performed such that an inner lead of a tape is separated from the chip main face as a modified example of this embodiment mode.

FIG. 7 is a plan view showing the memory TCP when the memory TCP is laminated as a modified example of this embodiment mode.

FIGS. 8A and 8B are respectively a plan view and a cross-sectional view showing the memory TCP when the memory TCP has a lead projected from the tape as a modified example of this embodiment mode.

FIGS. 9A, 9B and 9C are respectively a plan view, a cross-sectional view and a plan view showing the memory TCP when a one-layer taper is used as a modified example of this embodiment mode.

FIGS. 10A and 10B are respectively a plan view and a rear view showing the memory TCP of a structure in which a capacitor is mounted onto a chip mounting face of the tape as a modified example of this embodiment mode.

FIG. 11 is a plan view showing the memory TCP of a structure having a support lead in the tape as a modified example of this embodiment mode.

FIGS. 12A and 12B are respectively a plan view and a cross-sectional view showing the memory TCP of a structure having a frame in a tape 34 as a modified example of this embodiment mode.

FIGS. 13A and 13B are respectively a plan view and a cross-sectional view showing the memory TCP of a structure having a metallic plate on a chip as a modified example of this embodiment mode.

FIG. 14 is a plan view showing the memory TCP of a structure having display for recognizing the direction of a package and its position at a bonding time in the tape as a modified example of this embodiment mode.

FIGS. 15A and 15B are respectively a plan view and a rear view showing a semiconductor module loaded with the semiconductor device of this embodiment mode.

FIGS. 16A and 16B are respectively a plan view and a rear view showing a memory module of a registered DIMM as a modified example of this embodiment mode.

FIGS. 17A and 17B are respectively a plan view and a rear view showing a memory module of a SODIMM as a modified example of this embodiment mode.

FIGS. 18A, 18B and 18C are respectively a cross-sectional view and a partially enlarged sectional view showing a memory module laminated and mounted by a tape-on-tape structure, and a plan view showing the memory TCP at an upper stage as a modified example of this embodiment mode.

FIGS. 19A and 19B are respectively a cross-sectional view and a partially enlarged sectional view showing a memory module laminated and mounted by a lead-on-tape structure as a modified example of this embodiment mode.

FIGS. 20A and 20B are respectively a cross-sectional view and a partially enlarged sectional view showing a memory module laminated and mounted by a lead-on-board structure as a modified example of this embodiment mode.

FIGS. 21A and 21B are respectively a cross-sectional view and a partially enlarged sectional view showing a memory module laminated and mounted by the lead-on-board structure on both faces of a substrate as a modified example of this embodiment mode.

FIGS. 22A, 22B and 22C are respectively a side view and a schematic perspective view showing the connection of a signal terminal of an independent signal in the memory module laminated and mounted by the lead-on-board structure on both the faces of the substrate, and a plan view showing the memory TCP as a modified example of this embodiment mode.

FIG. 23 is a plan view showing the memory module of a structure in which an arrangement of the memory TCP is changed as a modified example of this embodiment mode.

FIG. 24 is a plan view showing the memory module of an unbuffered DIMM (2-bank 8-bit type) as a modified example of this embodiment mode.

FIG. 25 is a flow diagram showing a manufacturing process of the semiconductor device of this embodiment mode.

FIG. 26 is a flow diagram showing a manufacturing process of the semiconductor module loaded with the semiconductor device of this embodiment mode.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments modes of the present invention will next be explained in detail on the basis of the drawings. In all figures for explaining the embodiment modes, the same reference numerals are designated to the same members, and their repetitious explanations are omitted.

FIG. 1 is a block diagram showing the relation of a semiconductor device in one embodiment mode of the invention and a semiconductor module loaded with this semiconductor device. FIGS. 2 and 3 are respectively plan and sectional views showing the semiconductor device of this embodiment mode. FIG. 4 is a view of front and rear face patterns showing a two-layer tape. FIG. 5 is a plan view showing a main face of a chip. FIGS. 6 to 14 are explanatory views showing modified examples of the semiconductor device. FIG. 15 is a plan view and a rear view showing the semiconductor module loaded with the semiconductor device of this embodiment mode. FIGS. 16 to 24 are explanatory views showing modified examples of the semiconductor module. FIGS. 25 and 26 are flow diagrams showing manufacturing processes of the semiconductor device and the semiconductor module loaded with the semiconductor device.

First, one example of the relation of the semiconductor device of this embodiment mode and the semiconductor module loaded with this semiconductor device will be explained by FIG. 1. For example, the semiconductor module shown in FIG. 1 is an unbuffered DIMM (Dual In-line Memory Module) of 64-bit 2-bank, and can be constructed by a collection of four chips such as A and B, i.e., A: 1-bank 16-bit type and B: 2-bank 8-bit type. Similarly, the semiconductor module can be also constructed by a 1-bank 8-bit type and a 2-bank 4-bit type in a collection of two chips, or a 1-bank 32-bit type and a 2-bank 16-bit type in a collection of eight chips. A collection portion of these chips constituting the semiconductor module in FIG. 1 can be formed as one semiconductor module. In the following description, features of the 1-bank 16-bit type of a multi-chip module of four chips will be mainly explained as an example.

In FIG. 1, each of reference numerals D0 to D31 designates a chip. A clock enable signal CKE1 is supplied to chips D16 to D31 as CKE. A clock enable signal CKE0 is supplied to chips D0 to D16 as CKE. Address signals A0 to A13 are supplied to chips D0 to D31. A low address strobe signal /RAS is supplied to chips D6 to D31. A column address strobe signal /CAS is supplied to chips D0 to D31. A write enable signal /WE is supplied to chips D0 to D31. A power electric potential Vdd is supplied to chips D0 to D31. A ground electric potential Vss is supplied to chips D0 to D31. Further, a chip select signal /S0 is supplied to chips D0 to D3, and D8 to D11. A chip select signal /S1 is supplied to chips D16 to D19, and D24 to D27. A chip select signal /S2 is supplied to chips D4 to D7, and D12 to D15. A chip select signal /S3 is supplied to chips D20 to D23, and D28 to D31.

Further, input-output data DQ0 to DQ3 are set to input-output data of chips D0 and D16. Input-output data DQ4 to DQ7 are set to input-output data of chips D1 and D17. Input-output data DQ8 to DQ11 are set to input-output data of chips D2 and D18. Input-output data DQ12 to DQ15 are set to input-output data of chips D3 and D19. Input-output data DQ16 to DQ19 are set to input-output data of chips D4 and D20. Input-output data DQ20 to DQ23 are set to input-output data of chips D5 and D21. Input-output data DQ24 to DQ27 are set to input-output data of chips D6 and D22. Input-output data DQ28 to DQ31 are set to input-output data of chips D7 and D23. Input-output data DQ32 to DQ35 are set to input-output data of chips D8 and D24. Input-output data DQ36 to DQ39 are set to input-output data of chips D9 and D25. Input-output data DQ40 to DQ43 are set to input-output data of chips D10 and D26. Input-output data DQ44 to DQ47 are set to input-output data of chips D11 and D27. Input-output data DQ48 to DQ51 are set to input-output data of chips D12 and D28. Input-output data DQ52 to DQ55 are set to input-output data of chips D13 and D29. Input-output data DQ56 to DQ59 are set to input-output data of chips D14 and D30. Input-output data DQ60 to DQ63 are set to input-output data of chips D15 and D31.

Further, a data mask signal DQM0 is set to a signal of chips D0, D1, D16 and D17. A data mask signal DQM1 is set to a signal of chips D2, D3, D18 and D19. A data mask signal DQM2 is set to a signal of chips D4, D5, D20 and D21. A data mask signal DQM3 is set to a signal of chips D6, D7, D22 and D23. A data mask signal DQM4 is set to a signal of chips D8, D9, D24 and D25. A data mask signal DQM5 is set to a signal of chips D10, D11, D26 and D27. A data mask signal DQM6 is set to a signal of chips D12, D13, D28 and D29. A data mask signal DQM7 is set to a signal of chips D14, D15, D30 and D31.

One example of the construction of the semiconductor device of this embodiment mode will next be explained by FIG. 2 (a plan view) and FIG. 3 (a cross-sectional view taken along line X-X' of FIG. 2). The semiconductor device of this embodiment mode is constructed by a memory TCP of four chips (1-bank 16-bit type) shown in FIG. 1 and loaded with plural chips in one tape. This memory TCP is constructed by a tape 1 of one two-layer wiring layer structure, four chips 2 mounted to this tape 1, etc. Common signal terminals 3 are arranged on one set of two opposed sides of the tape. An independent signal terminal 4 is arranged on another side of the tape. The common signal terminals 3 on the two sides are electrically connected to each other by common signal wiring.

For example, the tape 1 is constructed by a two-layer tape in which wiring patterns 6 and 7 are formed on front and rear faces of an insulating basic material 5. For example, as shown in FIG. 4 (FIG. 4A shows the front face and FIG. 4B shows the rear face), the wiring patterns of the common signal wiring 8 and independent signal wiring 9 are formed on the front face of the insulating basic material 5 without crossing these wiring patterns on the same face. A ground electric potential plane pattern 10 and a power electric potential plane pattern 11 are formed on the rear face of the insulating basic material 5. The wiring patterns on the front face and the plane patterns on the rear face requiring electric conduction, and the front and rear faces of the common signal terminal 3 and the independent signal terminal 4 are connected to each other by through holes (via hole & land) 12. For example, this tape 1 is constructed by a tape member in which the insulating basic material 5 is formed by polyimide resin, etc. as one example. Wiring patterns 6, 7 are constructed by a metallic thin film such as a copper foil. The wiring patterns on the front and rear faces are coated with insulating coat materials 13, 14 such as polyimide resin to prevent a short circuit on a chip main face, or protect the wiring patterns from an external environment.

This tape 1 is approximately formed in a rectangular plane shape. The common signal terminals 3 are arranged on the front and rear faces on two opposed short sides of this tape 1 (both sides in FIG. 2). The independent signal terminals 4 are arranged on the front and rear faces on one long side (downward in FIG. 2) of the tape 1. The common signal terminals 3 on the two sides are commonly connected to each other across each chip 2 on the front face by each common signal wiring 8 extending in a long side direction. The independent signal terminals 4 on the one side are independently connected by each independent signal wiring 9 every chip 2. Four opening portions 15 are formed in this tape 1 in accordance with a mounting position of each chip 2. Each chip 2 and an inner lead 16 of the tape 1 are connected to each other through each opening portion 15. For example, a copper foil is plated with gold in a portion of this inner lead 16 as one example. The common signal terminal 3 and the independent signal terminal 4 become an outer lead 17.

There are a terminal for inputting the address signals A0 to A13, the chip select signal /CS, the low address strobe signal /RAS, the column address strobe signal /CAS, the write enable signal /WE, the clock enable signal CKE, the clock signal CLK, etc., and a terminal for supplying the ground electric potential Vss, the power electric potential Vdd, etc. as the common signal terminal 3. There is a terminal for inputting and outputting the input-output data DQ, the data mask signal DQM, etc. as the independent signal terminal 4.

In this tape 1, the common signal terminal 3 and the independent signal terminal 4 are arranged with left-right mirror symmetry with respect to a cut line 18 to the long side. Namely, the common signal terminals 3 are arranged in parallel with each other at the same interval on the two opposed short sides, and the independent signal terminals 4 are arranged at the same interval on the left-hand and right-hand sides of a long side. Thus, two memory TCPs loaded with chips 2 two by two can be manufactured by cutting the tape 1 along the cut line 18.

For example, each chip 2 is constructed by a memory chip such as a DRAM, and a memory circuit is formed within the chip. For example, as shown in FIG. 5, a pad 19 for drawing-out an electrode of this memory circuit to the exterior is arranged in a line on a main face in a central portion along the long side direction so that a so-called center pad structure is formed. In the pad 19 arranged in a line in each chip 2, a pad for a common signal connected to the common signal wiring 8 of the tape 1 is arranged far from the independent signal terminal 4, and a pad for an independent signal connected to the independent signal wiring 9 is arranged near the independent signal terminal 4.

In the memory TCP constructed above, in electric connection of the tape 1 and each chip 2, the chip 2 is mounted such that the main face of the chip 2 is arranged on a wiring layer side of the inner lead 16 of the tape 1. The pad 19 of each chip 2 and the inner lead 16 corresponding to each chip 2 of each common signal wiring 8 extending in the long side direction on the tape 1 are co