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Plane switching mode liquid crystal display device
   
Document Number
US Patent 6757042
Issued Date
June 29, 2004
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Abstract
An in-plane switching mode LCD device is disclosed, in which high response time is obtained and residual images are prevented from occurring. The in-plane switching mode LCD device includes first and second substrates, common electrodes arranged on one of the two substrates in a substantially zigzag pattern, a pixel electrode arranged with a substantially zigzag pattern corresponding to the common electrodes roughly in parallel with the common electrodes, common electrode frames projected from a bent portion of the common electrodes, pixel electrode frames projected from a bent portion of the pixel electrodes, and a liquid crystal between the first and second substrates.
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Number of Claims:
8
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Owner
Published
June 29, 2004
Application Number
09/938,563
Filed
August 27, 2001
US Classification
349/142   349/139 349/141
Int'l Classification
G02F   1/1343   (20060101)   G02F   1/13   (20060101)   G02F   1/1333   (20060101)   G02F   1/1339   (20060101)  
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Assistant Examiner
Attorney/Law Firm
Priority Data
Aug 29, 2000 [KR] 2000-50430
USPTO Field of Search
349/139   349/141   349/142  
Related Patents
7502086 - In-plane switching mode liquid crystal display device and method for manufacturing the same - Owned by LG DIsplay Co., Ltd. (Seoul,KR)

In an IPS mode LCD device and method, a plurality of sub-blocks are utilized to maintain a maximum transmittance even when a voltage above a predetermined value is applied to the device. The IPS mode LCD device includes a common electrode including a plurality of first segments and a plurality of second segments to define a plurality of blocks, wherein the plurality of first segments are formed substantially parallel to the gate line in the pixel region, and the plurality of second segments are formed substantially parallel to the data line, and connected to the first segments; and a pixel electrode including a plurality of third segments and at least one fourth segment, and being connected with a drain electrode of the thin film transistor, wherein each of the third segments is positioned between the first segments, and the at least one fourth segment connects the third segments.

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