An apparatus, system, and method for testing packet-based semiconductor devices by using simplified test data packets. Simplified test data packets are generated by conventional memory testers in one format. The simplified test data packets are realigned to another, different format by test mode circuitry located on an integrated circuit chip, test interface, or tester prior to testing the memory device. The test method potentially reduces the number of pieces of data which must be generated using an algorithmic pattern generator on a per-pin basis. Furthermore, the test method potentially reduces the number of packet words that has a combination of data generated from an APG and vector memory. Packet-based semiconductor devices are also disclosed.
CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation of application Ser. No. 09/146,629, filed Sep. 3, 1998, now U.S. Pat. No. 6,374,376 B1, issued Apr. 16, 2002.
