A method and system by which multiple ADC architectures can be emulated comprises, a number of electrical components commonly used in a variety of ADC architectures, routing an analog input through a number of switches, and selectively connecting and disconnecting the switches to emulate one of multiple possible ADC architectures.
RELATED APPLICATIONS
This application claims priority under 35 U.S.C. .sctn. 119(e) from previously-filed provisional patent application No. 60/343,090, filed Dec. 21, 2001, entitled "Programmable Architecture ADC [Analog-to-Digital Converter]" which is incorporated herein by reference in its entirety.
A multi-mode analog to, digital converter (ADC). The novel ADC includes an input terminal for receiving an analog input signal; a plurality of processing stages, each processing stage adapted to generate an output signal from an input to that processing stage; and a mechanism for determining a mode of operation and in accordance therewith connect the processing stages and the input terminal in a predetermined configuration. In an illustrative embodiment, the ADC can be configured as a subranging ADC, and the mechanism for determining, the mode of operation includes a signal processor for automatically selecting the mode of operation based on the frequency components of the input signal.
Novel system and methodology for sampling analog input signals to reduce an average common-mode input current caused by unbalanced nodes of an input signal source. An analog-to-digital (A/D) conversion system for converting an analog input signal supplied by a signal source having first and second nodes may have a first sampling circuit coupled to the first node for sampling the input signal with respect to a reference signal and configured so as to provide a substantially zero total charge taken from the first node during a first sampling process, and a second sampling circuit coupled to the second node for sampling the input signal with respect to the reference signal and configured so as to provide a substantially zero total charge taken from the second node during a second sampling process. In response to first and second output signals respectively produced by the first and second sampling circuits, an output circuit may provide common-mode rejection.
A system for emulating characteristics of a plurality of analog-to-digital converter (ADC) architectures in the conversion of an analog signal to a digital signal. The system comprises a flash ADC for sampling the analog signal and outputting a digital representation of a sample of the analog signal, a digital-to-analog converter (DAC) for supplying the reference values to the flash ADC, and a digital signal processor (DSP) for processing the digital representation of the sample and outputting the digital signal. The digital representation is based on a comparison of the sample to reference values and comprising a number of bits of resolution. The DSP is configured to send a modifiable control signal defining the reference values to the DAC.
A novel sampling system having a sampling device responsive to an analog input signal and a reference signal for providing corresponding charges. A switching circuit is provided to supply the input signal and the reference signal to the sampling device. The switching circuit is controlled to supply the input signal and the reference signal to the sampling device so as provide a substantially zero total charge taken by the sampling device from a source of the input signal. One application of the foregoing is in analog-to-digital conversion.
A pipeline ADC has a plurality of analog-to-digital conversion units cascaded in series to form a pipeline. An error correcting method for the pipeline ADC includes during a first mode, measuring the plurality of analog-to-digital conversion units utilizing an extra analog-to-digital conversion module; calculating a plurality of correction constant sets according to digital output values of the extra analog-to-digital conversion module in the measuring step; and during a second mode, correcting output signals of the plurality of analog-to-digital conversion units according to the correction constant sets.
