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Circuit for looping serial bit streams from parallel memory
   
Document Number
US Patent 6766411
Issued Date
July 20, 2004
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Abstract
A circuit for generating one or more serial bit streams includes a memory coupled to a reformatter, which is in turn coupled to a serializer for converting parallel data to serial data. The memory includes a plurality of words having a known bit width (e.g., 32 bits) for storing one or more serial bit streams. The length of each serial bit stream is generally not an integer multiple of the memory's bit width, causing the last word storing each serial bit stream to contain a gap. The reformatter eliminates each such gap by combining bits from the last word of a bit stream with bits from the first word to provide a completely filled word to the serializer. As operation proceeds, the reformatter continues to combine bits from successive words to ensure that completely filled words are produced. Gaps that formerly appeared when producing serial bit streams are thereby eliminated.
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Number of Claims:
20
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Owner
Teradyne, Inc. (Boston, MA)
Published
July 20, 2004
Application Number
10/170,122
Filed
June 12, 2002
US Classification
711/109   341/101 370/366 711/110 714/738
Int'l Classification
G06F   12/00   (20060101)  
Examiner
USPTO Field of Search
711/109   711/110   370/100   370/366   714/718   714/738   341/95   341/100   341/101  
Related Patents
7529149 - Memory system and method with serial and parallel modes - Owned by MOSAID Technologies Incorporated (Kanata, Ontario,CA)

Methods and systems are provided that allow the method of access to one or more memory banks to be performed using serial access, or using parallel access. In serial mode, each link operates as an independent serial link. In contrast, during serial mode, the links operate in common as a parallel link. Where input and output controls are received independently for each link for serial mode, a single set of input and output controls is used in common by all of the links during parallel mode.

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