To reduce the effect of the phase shift error originated from the mismatch of the delay units of the clock generator, we propose to add one more set of averaging amplifiers and averaging impedances, such as resistors, into the circuit of the clock generator. In the clock generator, outputs of all delay units connect to inputs of all averaging amplifiers respectively, and the averaging impedances connect the corresponding outputs of two adjacent averaging amplifiers, so as to form a closed loop. When a phase shift error occurs in the delay units, the averaging current through the averaging impedances will decrease the phase shift error in each stage. Specifically, the output impedance of the averaging amplifiers approaches infinite, and thus the resistance of the averaging impedances is relatively small. Therefore almost all signal currents will go through the averaging impedances, and an optimal averaging effect is achieved. In addition, we apply the simple voltage-mode phase interpolation technique to the averaging impedances for better phase resolution and more output phases. Further, utilizing the folding architecture, our proposed clock generator can output high-frequency clock signals at low-frequency operating clock.
A multiphase voltage controlled oscillator includes at least one ring oscillating unit and a resistor ring; the ring oscillating unit is formed by connecting a plurality of phase-delay elements in cascade and the resistor ring is formed by connecting a plurality of resistor elements in cascade; wherein the connecting nodes of each ring oscillating unit are electrically connected to the connecting nodes of the resistor ring such that the ring oscillating unit can generate a plurality of oscillating signals with uniform phase differences.
Disclosed are multiphase oscillators comprising a plurality of delay stages serially coupled in a loop by a plurality of nodes, with the loop being folded to provide two concentric rings of delay stages with equal numbers of allocated nodes. A second plurality of negative-resistance elements are provided, each element having a first output coupled to a node on the first concentric ring and a second output coupled to a node on the second concentric ring. Each such output switches between first and second voltage levels, and provides a negative resistance to a signal coupled to it during at least a portion of the transition between voltage levels. The outputs of an element switch to opposite voltage levels. With this construction, a high-voltage pulse propagates around the loop of delay stages, with a low-voltage pulse propagating behind it. Also disclosed are circuits to control the direction of pulse propagation.
