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Claims  |
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What is claim is:
1. A DDR and QDR converter, comprising:
a QDR interface, to perform a signal exchange with a QDR device;
a DDR interface, to perform a signal exchange with a DDR device;
a clock controller, to convert a clock signal output from the QDR device
into an operation clock signal used by the DDR and QDR converter and the
DDR device;
a state register set, to store a QDR device state;
a data converter, to convert a QDR data format into an appropriate DDR data
format, and to convert a DDR data format into an appropriate QDR data
format; and
a command controller, to obtain a QDR command signal from the QDR device
and process the QDR command signal into a corresponding DDR command signal
output to the DDR device.
2. The DDR and QDR converter of claim 1, wherein the data converter
comprises:
a data mask and probe controller, to obtain a QM signal and a DQS signal of
the QDR device, and to convert the QM signal into a DDR QM signal output
to the DDR device, and to convert the DQS signal into a data extraction
signal for the QDR device to extract data from the DDR device;
a QDR-to-DDR data converter, to convert a serial signal of the QDR device
into parallel signals, and to transmit the parallel signals into two DDR
devices individually according to a command of the command controller; and
a DDR-to-QDR data converter, to convert data signals of the DDR devices
into a serial signal used by the QDR device, and to transmit the serial
signal into the QDR device according to the command of the command
controller.
3. The DDR and QDR converter of claim 1, wherein the data converter further
comprises:
a data mask and probe controller, to obtain a QM signal and a DQS signal of
the QDR device, and to convert the QM signal into a DDR QM signal output
to the DDR device, to convert the DQS signal into a data extraction signal
for the QDR device to extract data from the DDR device, and to return the
DQS signal according to two times the clock signal when the DQS signal has
to be retransmitted back to the QDR device;
a QDR-to-DDR data converter, to convert a serial signal of the QDR device
into parallel signals, and to transmit the parallel signals into two DDR
devices individually according to a command of the command controller; and
a DDR-to-QDR data converter, to convert data signals of the DDR devices
into a serial signal used by the QDR device, and to transmit the serial
signal into the QDR device according to the command of the command
controller.
4. The DDR and QDR data converter of claim 1, wherein the data converter
comprises:
a phase lock loop, to receive the clock signal and to generate an internal
operation clock signal with a frequency double a frequency of the clock
signal;
a data mask and probe controller, to obtain a QM signal and a DQS signal of
the QDR device, and to convert the QM signal into a DDR QM signal output
to the DDR device, and to convert the DQS signal into a data extraction
signal for the QDR device to extract data from the DDR device and to
return the DQS signal according to the internal operation clock signal
when the DQS signal has to be retransmitted back to the QDR device;
a QDR-to-DDR data converter, to convert a serial signal of the QDR device
into parallel signals, and to transmit the parallel signals into two DDR
devices individually according to a command of the command controller; and
a DDR-to-QDR data converter, to convert data signals of the DDR devices
into a serial signal used by the QDR device, and to transmit the serial
signal into the QDR device according to the command of the command
controller.
5. A DDR and QDR converter, applied between a QDR interface and a DDR
interface, wherein the QDR interface is used to perform a signal exchange
with a QDR device, and the DDR interface is used to perform a signal
exchange with a DDR device, the DDR and QDR converter comprising:
a clock controller, to receive a clock signal output from the QDR device,
and to convert the clock signal into a clock signal used by the DDR and
QDR converter;
a command controller, to receive a QDR command signal of the QDR device and
to convert the command signal into a corresponding DDR command signal
output to the DDR device; and
a data converter, coupled to the QDR interface, the DDR interface and the
command controller, to convert a QDR data format into an appropriate DDR
data format, and to convert a DDR data format into an appropriate QDR data
format.
6. The DDR and QDR converter of claim 5, wherein the data converter
comprises:
a data mask and probe controller, to obtain a QM signal and a DQS signal of
the QDR device, and to convert the QM signal into a DDR QM signal output
to the DDR device, and to convert the DQS signal into a data extraction
signal for the QDR device to extract data from the DDR device;
a QDR-to-DDR data converter, to convert a serial signal of the QDR device
into parallel signals, and to transmit the parallel signals into two DDR
devices individually according to a command of the command controller; and
a DDR-to-QDR data converter, to convert data signals of the DDR devices
into a serial signal used by the QDR device, and to transmit the serial
signal into the QDR device according to the command of the command
controller.
7. The DDR and QDR converter of claim 5, wherein the data converter further
comprises:
a data mask and probe controller, to obtain a QM signal and a DQS signal of
the QDR device, and to convert the QM signal into a DDR QM signal output
to the DDR device, to convert the DQS signal into a data extraction signal
for the QDR device to extract data from the DDR device, and to return the
DQS signal according to two times of the clock signal when the DQS signal
has to be retransmitted back to the QDR device;
a QDR-to-DDR data converter, to convert a serial signal of the QDR device
into parallel signals, and to transmit the parallel signals into two DDR
devices individually according to a command of the command controller; and
a DDR-to-QDR data converter, to convert data signals of the DDR devices
into a serial signal used by the QDR device, and to transmit the serial
signal into the QDR device according to the command of the command
controller.
8. The DDR and QDR data converter of claim 5, wherein the data converter
comprises:
a programmable logic array, to receive the clock signal and to generate a
return clock signal with a frequency double a frequency of the clock
signal;
a data mask and probe controller, to obtain a QM signal and a DQS signal of
the QDR device, and to convert the QM signal into a DDR QM signal output
to the DDR device, and to convert the DQS signal into a data extraction
signal for the QDR device to extract data from the DDR device and to
return the DQS signal according to the return clock signal when the DQS
signal has to be retransmitted back to the QDR device;
a QDR-to-DDR data converter, to convert a serial signal of the QDR device
into parallel signals, and to transmit the parallel signals into two DDR
devices individually according to a command of the command controller; and
a DDR-to-QDR data converter, to convert data signals of the DDR devices
into a serial signal used by the QDR device, and to transmit the serial
signal into the QDR device according to the command of the command
controller.
9. A DDR and QDR converter, comprising:
a QDR interface, used to perform a signal exchange with a QDR device;
a DDR interface, used to perform a signal exchange with a DDR device;
a conversion core, to convert a QDR command and data format into a DDR
command and data format sent to the DDR device via the DDR interface, and
to convert a DDR command and data format into a QDR command and data
format sent to the QDR device via the QDR interface.
10. An interface card using a DDR and QDR converter, applied to a circuit
board supporting a QDR module, the circuit comprising at least a chip set
that support the QDR module, the interface card comprising:
at least a DDR module array; and
a DDR and QDR converter, comprising:
a QDR interface, to perform a signal exchange with the chip set;
a DDR interface, to perform a signal exchange with the DDR module array;
and
a conversion core, to convert a QDR command and data format into a DDR
command and data format output to the DDR module array via the DDR
interface, and to convert a DDR command and data format into a QDR command
and data format output to the chip set that support the QDR module via the
QDR interface.
11. A motherboard using a DDR and QDR converter, comprising:
a chip set, to support a QDR module; and
a DDR and QDR converter, further comprising:
at least a DDR DIMM;
a DDR and QDR converter, having a QDR interface to perform a signal
exchange with the chip set, a DDR interface, to perform a signal exchange
with the DDR DIMM, and a conversion core, to convert a QDR command and
data format into a DDR command and data format output to the DDR DIMM via
the DDR interface, and to convert a DDR command and data format into a QDR
command and data format output to the chip set that support the QDR module
via the QDR interface.
12. A memory module using a DDR and QDR converter, applied to a memory that
supports a QDR memory module, the memory module comprising:
at least a DDR memory chip set array; and
a DDR and QDR converter, having a QDR interface to perform a signal
exchange with the memory, a DDR interface, to perform a signal exchange
with the DDR memory chip set array, and a conversion core, to convert a
QDR command and data format into a DDR command and data format output to
the DDR memory chip set array via the DDR interface, and to convert a DDR
command and data format into a QDR command and data format output to the
memory.
13. A memory module interface using a DDR and QDR converter, comprising:
at least a DDR DMM; and
a DDR and QDR converter, having a QDR interface to perform a signal
exchange with the memory module interface, a DDR interface, to perform a
signal exchange with the DDR DIMM, and a conversion core, to convert a QDR
command and data format into a DDR command and data format output to the
DDR DIMM via the DDR interface, and to convert a DDR command and data
format into a QDR command and data format output to the memory module
interface.
14. A portable computer motherboard using a DDR and QDR converter,
comprising:
a chip set that support a QDR module; and
a DDR and QDR converter, having a QDR interface to perform a signal
exchange with the chip set, a DDR interface providing at least a SO-DIMM
slot, and a conversion core, to convert a QDR command and data format into
a DDR command and data format output to the SO-DIMM slot via the DDR
interface, and to convert a DDR command and data format into a QDR command
and data format output to the chip set via the QDR interface. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates a memory converter and the apparatus for applying the
same. More particularly, the invention relates to a DDR and QDR converter,
and an interface, a motherboard, a memory module and a portable computer
motherboard using the DDR and QDR converter.
2. Description of the Related Art
Along with the advancement in techniques for wafer fabrication and package
process, and in addition to the rapid growth in processing speed of the
central processing unit (CPU), various alterations of a computer's memory
management have occurred. Demand for access speed has pushed the
development of memory from the early dynamic random access memory (RAM),
the extended data output random access memory (EDO RAM), to the current
synchronous data rate RAM (SDR RAM) and double data rate RAM (DDR RAM).
The enhancement of access speed of the memory has caused a higher
fabrication cost for various kinds of RAM's.
SUMMARY OF THE INVENTION
The present invention provides a method and a structure with a higher
access speed compared to the current memory to significantly improve the
efficiency of the DDR RAM's without incurring high fabrication cost. The
structure is called "quadruple data rate RAM (QDR)". The invention
includes the formation of the ADR signal system and the conversion method
between the DDR and QDR signal systems. The conversion structure and
method provided by the invention can be applied to all the electronic
equipment that requires RAM, such as interface cards, motherboards and
portable computer motherboards.
The DDR and QDR converter provided by the invention has a QDR interface, a
DDR interface, a clock controller, a command controller, a state register
and a data converter. The QDR interface is used to exchange a signal with
a QDR device. The DDR interface is used to exchange a signal with a DDR
device. The clock controller converts the clock signal sent from the QDR
device into a clock used by the converter and the DDR device. After
receiving a QDR command signal from the QDR device, the command controller
processes the QDR command signal into a corresponding DDR command signal
and outputs the DDR command signal into the DDR device. The state register
is used to store data of the mode register set (MRS) and the extended mode
register set (EMRS), and to provide conversion data to the command
controller for appropriate command and data conversion. The data converter
is used to convert the QDR data format into a DDR data format, and convert
the DDR data format into a QDR data format.
In one embodiment of the invention, the data converter comprises a data
mask and probe controller, a QDR-to-DDR data converter and a DDR-to-QDR
data converter. The data mask and probe controller is used to obtain the
QM signal and DQS signal of the QDR device. The QM signal is then
converted into a DDR QM signal output to the DDR device, while the DQS
signal is converted into a data extract signal for the QDR device to
extract data from the DDR device. The QDR-to-DDR data converter converts
the serial signal of the QDR device into a parallel signal. According to
the command of the command controller, the parallel signal is sent to two
DDR devices. The DDR-to-QDR data converter converts two data signals of
the DDR device into the serial signals used by the QDR device, which are
then sent to the QDR device according to the command output from the
command controller.
According to the above, a conversion channel is established between QDR and
DDR, so that DDR can operate normally in a system or apparatus supporting
QDR without converting the system or apparatus into a DDR supporting
system or apparatus. The DDR and QDR can thus operate normally
simultaneously.
Therefore, the user does not have to buy an additional QDR memory module.
The invention uses the existent DDR memory module to upgrade to a memory
module with both the DDR and QDR functions.
For the manufacturer, DDR chips with a lower cost can be selected while
manufacturing the interface, motherboard and related printed circuit
boards to obtain a product with the QDR data process effect. The quality
and performance of the product are enhanced without raising the
fabrication cost.
Both the foregoing general description and the following detailed
description are exemplary and explanatory only and are not restrictive of
the invention, as claimed.
BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWING
These, as well as other features of the present invention, will become more
apparent upon reference to the drawings, wherein:
FIG. 1A shows a block diagram of a converter in a first embodiment of the | | |
