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Combinational test pattern generation method and apparatus
   
Document Number
US Patent 6782502
Issued Date
August 24, 2004
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Abstract
A method and apparatus that couple a change input scan chain test pattern with an initialization scan chain test pattern such that a resultant scan chain test pattern is produced, and apply the resultant scan chain test pattern to at least one combinational logic path. In one embodiment, the coupling is achieved by interleaving the change input scan chain test pattern with the initialization scan chain test pattern. In another embodiment, the coupling is achieved by creating a constructed test pattern set from the change input and the initialization scan chain test pattern.
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Number of Claims:
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Owner
NEC Electronics, Inc. (Santa Clara, CA)
Published
August 24, 2004
Application Number
10/262,271
Filed
October 1, 2002
US Classification
714/738   714/731
Int'l Classification
G11B   20/18   (20060101)   G01R   31/28   (20060101)   G01R   31/3183   (20060101)  
Examiner
Attorney/Law Firm
Parent Case
CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 09/265,513, entitled "Combinational Test Pattern Generation Method and Apparatus", filed Mar. 10, 1999, now U.S. Pat. No. 6,480,980.
USPTO Field of Search
714/738   714/736   714/731   714/45   714/47   714/724   714/726   714/733   702/59   708/254   710/107   710/108   710/14   710/100   710/306  
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