Data storage and processing apparatus, and method for fabricating the same

What is claimed is:

1. A data storage and processing apparatus comprising:

ROM and/or WORM and/or REWRITABLE memory modules on a substrate; and/or

one or more processing modules on the substrate,

wherein the memory and/or processing modules are provided as a plurality of main layers formed vertically on top of the substrate, wherein each main layer of a memory module and/or processing module comprise functional sublayers, wherein the memory modules and/or processing modules in each main layer communicate through vias, surface or edge connections with other main layers and with circuitry provided on or in the substrate and wherein the apparatus comprises active components in the form of transistors and/or diodes for operating the apparatus, characterized in that at least some and at most all the transistors and/or diodes for operating the apparatus are provided on or in the substrate, and wherein each main layer comprises a combination of organic materials and inorganic materials.

2. Apparatus according to claim 1, characterized in that at least a portion of the substrate contains semiconducting materials in doped or undoped form provided in bulk or as thin film on a passive carrier, and where the semiconducting materials are selected from one or more of the following, viz. silicon, gallium arsenide and germanium in amorphous, polycrystalline, microcrystalline, bulk or process-defined single crystal form, or organic semiconducting materials including molecules, oligomers or polymers or combinations thereof.

3. Apparatus according to claim 1, characterized in that the circuitry provided on or in the substrate is realized by one or more of the following technologies, viz. CMOS, NMOS or PMOS.

4. Apparatus according to claim 1, characterized in that the circuitry provided on or in the substrate comprises one or more cache memories in the form of SRAM, DRAM and/or ferroelectric RAM (FERAM).

5. Apparatus according to claim 1, characterized in that it comprises thin-film circuitry.

6. Apparatus according to claim 1, characterized in that the circuitry provided on or in the substrate comprises processors for detection and correction on memory errors and defects.

7. Apparatus according to claim 1, characterized in that the circuitry provided on or in the substrate comprises processors for remapping defect memory regions in the overlying layers and/or the substrate.

8. Apparatus according to claim 1, characterized in that the circuitry provided on or in the substrate comprises processors for dynamically remapping the memory modules in order to optimize performance and lifetimes thereof.

9. A data storage and processing apparatus, comprising:

a substrate including an active circuitry, wherein the active circuitry includes at least one of one or more transistors and one or more diodes for operating the apparatus; and

a plurality of main layers above the substrate, wherein each main layer includes at least one of one or more memory modules and one or more processing modules;

wherein:

the memory and processing modules within each main layer communicate with memory and processing modules of other layers and with the active circuitry of the substrate through at least one of vias, surface connections, and edge connections of each main layer; and

each main layer includes a stack of one or more functional sublayers, with each functional sublayer realizing one or more specific circuit functions, wherein each functional sublayer comprises a combination of low temperature-compatible organic thin-film materials and low temperature-compatible processed inorganic thin-film materials, and wherein each main layer includes a portion of the active circuitry.

10. The apparatus according to claim 9, wherein at least one of the main layers comprises memory modules with passive matrix-addressable memory elements defined in a memory material at crossings between electrodes of a first set of parallel electrodes provided on a surface of the memory material and a second set of parallel electrodes provided on an opposite surface of the memory material and in intersecting relationship with the first set of electrodes, the memory elements being realized as non-linear impedance elements at the crossings, and each memory element is provided with a logic value given by an electrical impedance.

11. The apparatus according to claim 10, wherein each non-linear impedance element is one of a rectifying diode and a thin-film transistor.

12. The apparatus according to claim 11, wherein the non-linear impedance elements are made of at least one of the following:

at least one of silicon, gallium arsenide and germanium in at least one of the forms of amorphous, polycrystalline, microcrystalline, bulk, and process-defined single crystal; and

organic semiconducting materials including at least one of molecules, oligomers, and polymers, and combinations thereof.

13. The apparatus according to claim 10, wherein at least one main layer comprises dual passive matrix-addressable memory modules in separate sublayers, one overlying and one underlying memory module sharing one set of row or column electrodes.

14. The apparatus according to claim 10, wherein a plurality of main layers is provided and wherein at least two of the main layers share at least one of common row and column drive electronics and share optional sense electronics connected therewith through common wires.

15. The apparatus according to claim 9, wherein a plurality of main layers is provided, wherein each main layer includes a plurality of memory modules, the memory modules being in the form of juxtaposed segments stacked on the top of other juxtaposed segments in the main layer to form two or more juxtaposed stacks on the substrate, and that a part of each segment in each stack is connected to a portion of the substrate and communicates electrically with the active circuitry provided thereon.

16. The apparatus according to claim 9, wherein a plurality of main layers is provided, wherein each main layer includes a plurality of memory modules, the memory modules being provided in the form of juxtaposed segments stacked on the top of other juxtaposed segments in the main layer in a staggered arrangement such that each memory module in the stack is provided staggered in relation to adjacent neighbor modules, and that a part of each segment in each stack is connected to a portion of the substrate and communicates electrically with the active circuitry provided thereon.

17. The apparatus according to claim 9, wherein a plurality of throughgoing electrical conductors or vias providing power and signal connections among the main layers and the substrate is distributed laterally in a staggered arrangement.

18. The apparatus according to claim 9, wherein each memory module is one of a ROM, a WORM, and a REWRITEABLE type.

19. The apparatus according to claim 18, wherein at least one memory is one of a masked ROM and a patterned ROM.

20. The apparatus according to claim 9, wherein at least one main layer includes memory modules of at least two of the ROM, WORM, and REWRITEABLE types.

21. The apparatus according to claim 9, wherein at least a portion of the substrate comprises circuitry which is electrically connected with one or more of the main layers.

22. The apparatus according to claim 21, wherein the active circuitry of the substrate is formed from one of doped and undoped semiconducting materials on a passive carrier in one of bulk and thin film form.

23. The apparatus of claim 21, wherein the semiconducting materials are selected from at least one of:

at least one of silicon, gallium arsenide and germanium in at least one of the forms of amorphous, polycrystalline, microcrystalline, bulk, and process-defined single crystal; and

organic semiconducting materials including at least one of molecules, oligomers, and polymers, and combinations thereof.

24. The apparatus according to claim 22, wherein the active circuitry is realized by one or more of CMOS, NMOS, and PMOS technologies.

25. The apparatus according to claim 22, wherein the active circuitry includes one or more cache memories in the form of at least one of SRAM, DRAM and ferroelectric RAM (FERAM).

26. The apparatus according to claim 22, wherein the active circuitry includes processors for detection and correction of errors and defects of the memory modules.

27. The apparatus according to claim 22, wherein the active circuitry includes processors for remapping defective memory modules.

28. The apparatus according to claim 22, wherein the active circuitry includes processors for dynamically remapping memory modules.

29. The apparatus according to claim 9, wherein the inorganic thin-film material is at least one of silicon, silicon compounds, metals, metal compounds, and any combination thereof.

30. The apparatus according to claim 9, wherein the active circuitry of the main layers is realized in thin-film technology.

31. A method for fabricating a data storage and processing apparatus including a substrate including an active circuitry, wherein the active circuitry includes at least one of one or more transistors and one or more diodes for operating the apparatus, and the apparatus also including one or more main layers above the substrate, wherein each main layer includes at least one of one or more memory modules and one or more processing modules, wherein the memory and processing modules within each main layer communicate with memory and processing modules of other layers and with the active circuitry of the substrate through at least one of vias, surface connections, and edge connections of each main layer; wherein each main layer includes a stack of one or more functional sublayers, with each functional sublayer realizing one or more specific circuit functions, wherein each function sublayer comprises a combination of low temperature-compatible organic thin-film materials and low temperature-compatible processes inorganic thin-film materials; and wherein each main layer includes a portion of the active circuitry, the method comprising:

depositing and processing the main layers and functional sublayers of each main layer thereof in successive steps, wherein:

the depositing step includes one or more of:

selecting from semiconductor materials among thin films of amorphous, polycrystalline or microcrystalline silicon or germanium, oxides, dielectric materials, metals or combinations thereof and depositing the layer of such material by one of sputtering, evaporation, chemical vapour deposition or plasma-assisted chemical vapour deposition, spin coating, and combinations thereof; and

selecting from polymer materials among molecular, oligomer, and polymer and depositing the layer of such material by one of solvent techniques, evaporation, sputtering, vacuum-based techniques, film transfer techniques, and combinations thereof; and

the processing step includes one or more of:

processing each deposited layer of semiconductor materials using one of photolithography, wet etching, dry etching, reactive ion etching, plasma etching, chemo-mechanical polishing, ion implantation, and combinations thereof; and

processing each deposited layer of polymer materials using transient heating with one of pulsed laser or particle beams for inducing crystallization of deposited amorphous films, grain refinement of deposited films, and incorporation and activation of dopants therein, wherein;

the deposited layer is processed under thermal conditions that avoid subjecting an already deposited and processed layer to a static temperature exceeding a temperature in a range of 150-450.degree. C.; and

the deposited layer is processed under thermal conditions that avoid subjecting an already deposited and processed layer to dynamic temperatures exceeding a transient stability limit of the polymer materials, wherein the transient stability limit is defined as one of being less than 500.degree. C. for not more than 10 ms and process-induced chemical damage.

32. The method according to claim 31, wherein fabricating a thin-film silicon-based circuitry and transistors is performed by a low-temperature compatible process using laser-induced crystallization and dopant activation of the thin-film transistors.

33. The method according to claim 31, wherein a memory module is realized as a matrix-addressable memory with isolation diodes, characterized by forming isolation diodes in one of vertical and planar configurations by depositing directly amorphous at least one of microcrystalline and polycrystallines n- and p-type silicon or germanium films and depositing directly semiconducting organic thin films of oligomer or polymer.

34. The method according to claim 31, wherein a memory module is realized as a matrix-addressable memory with isolation diodes, characterized by forming the isolation diodes by laser-induced melting and solidification of deposited n- and p-type amorphous or microcrystalline films of inorganic semiconducting material directly on underlying one or more low temperature-compatible layers.

35. The method according to claim 34, characterized by protecting the one or more underlying layers from reacting with molten semi conductor material during the laser-induced crystallization by providing a thin-film diffusion barrier.

36. The method according to claim 34, characterized by designing a reaction between a molten semiconductor material and the one or more underlying layers to form a stable electrical conducting compound.

37. The method according to claim 31, wherein a memory module is realized as a matrix-addressable memory with isolation diodes, characterized by:

forming the isolation diodes by laser-induced melting and solidification of deposited amorphous or microcrystalline inorganic film; and

forming a pn junction of the diodes with compensating doping, the pn junctions being realized either from one of a deposited layer on an underlying metallization and autodoping using alloying elements in a passive matrix metallization.

38. The method according to claim 31, wherein a memory module is realized as a matrix-addressable memory with isolation diodes, characterized by:

forming the isolation diodes by laser-induced melting and solidification of a deposited amorphous or microcrystalline inorganic film; and

forming a Schottky-barrier diode with one of an underlying metallization structure and a compound formed by a reaction with the underlying metallization structure.

39. The method according to claim 31, characterized by:

constraining the laser-induced crystallization within an explosive crystallization regime;

transient melting of the surface of the film;

forming self-propagating liquid film.

40. The method according to claim 31, characterized by forming isolating structures from high resistivity or anisotropic contact materials.

41. The method according to claim 40, characterized by inducing modification of the contact materials by one of chemical and thermal techniques to thereby realize both the isolation diode and the non-conductive interlayer dielectric.

42. The method according to claim 41, characterized by the chemically or thermally induced modification taking place respectively by autodoping of high-resistivity amorphous silicon and laser-induced crystallization of high resistivity amorphous silicon.

43. The method according to claim 31, wherein a memory module is realized as a matrix-addressable memory with isolation diodes, characterized by:

forming diodes in spatially limited regions, wherein the limited regions include intersections of the matrix and simultaneously providing lateral isolation between the diodes by using a self-aligned process;

limiting the formation of diode junctions to the spatially limited regions by one of laser-induced crystallization with modulation of absorbed laser energy by features of underlying layers or structures, laser-induced crystallization with modulation of absorbed laser energy by antireflective or reflective thin films, constraining nucleation during laser-induced crystallization to metal regions by controlling an interlayer dielectric surface, using underlying layers or structures as dopant sources for diode junction formation via explosive crystallization, and selective chemical or physical vapour deposition of amorphous or microcrystalline films effected by surface modification of an interlayer dielectric surface.

44. The method according to claim 31, characterized by separating the functional sublayers with planarized dielectric layers, wherein the dielectric layers are made of at least one of oligomer, polymer, and inorganic material.

45. The method according to claim 31, characterized by initiating the induced crystallization by directed energy sources other than lasers, including pulsed ion and electron beams.

46. A data storage and processing apparatus, comprising:

a substrate including an active circuitry, wherein the active circuitry includes at least one of one or more transistors and one or more diodes for operating the apparatus; and

one or more groups of memory planes, wherein each group includes a plurality of memory planes formed above the substrate, wherein for each group:

the plurality of memory planes are stacked,

a memory plane of the plurality is displaced in an X direction or Y direction or both in relation to another memory plane of the plurality, and

each memory plane of the plurality is configured to electrically communicate with the active circuitry of the substrate.

47. The apparatus according to claim 46, wherein:

the apparatus includes a plurality of groups of memory planes; and

each group is juxtaposed in relation to another group above the substrate.

48. The apparatus according to claim 47, wherein the memory planes electrically communicate with the active circuitry through at least one of vias, surface connections, and edge connections.

49. The apparatus according to claim 47, wherein the memory planes are formed from a combination of low temperature-compatible organic thin-film materials and low temperature-compatible processed inorganic thin-film materials, and wherein each main layer includes a portion of the active circuitry.

Description Submit all comments and votes

The present invention concerns a data storage and data-processing apparatus, as well as a method for fabricating the same.

The invention particularly concerns a data storage and data-processing apparatus 3D scalable single- and multilayer memory and data-processing modules and apparatus; and which even more particularly are based on ROM and/or WORM and/or REWRITABLE blocks addressed in a passive matrix scheme.

The present application claims priority from Norwegian Patent Application No. 982518 titled "Scalable integrated data-processing device", which has been assigned to the Assignee of the present invention and the disclosure of which is hereby additionally incorporated by reference. This scalable integrated data-processing device, particularly a microcomputer, comprises a processing unit with one or more processors and a storage unit with one or more memories. The data-processing device is provided on a carrier substrate and comprises mutually adjacent, substantially parallel layers stacked upon each other. The processing unit and the storage unit are each provided in one or more such layers and/or in layers formed with a selected number of processors and memories in selected combinations.

In each layer are provided horizontal electrical conducting structures which constitute internal electrical connections in the layer and besides each layer comprises further electrical conducting structures which provide electrical connections to other layers and to the exterior of the data processing device. These further electrical structures in a layer are provided on at least a side edge of the layer as electrical edge connections and/or preferably as vertical conducting structures which form an electrical connection in a cross-direction of the layer and perpendicular to its plane to contact electrical conducting structures in other layers.

In particular, the layers may be formed of a plurality of sublayers made of organic thin-film materials. Some of all layers or sublayers may also be made with organic or inorganic thin-film materials or both.

A preferred embodiment of the data-processing device according to the priority application is shown in FIG. 1. Advantageously are here processors and memories, the latter, e.g., RAMs assigned to the processors, provided in one and the same layer. A processor interface 3 with an I/O interface 8 is provided on a substrate S and above the processor interface 3 follows a processor layer P.sub.1 with one or more processors. Both the processor interface 3 and the processor layer P.sub.1 may as the lowermost layers in the data-processing device and adjacent to the substrate be realized in conventional, e.g., silicon-based technologies.

Above the processor layer P.sub.1 is provided a first memory layer M.sub.1 which may be configured with one or more RAMs 6 assigned to the processors 5 in the underlying processor layer P.sub.1. In FIG. 1, however, the separate RAMs 6 in the memory layer M.sub.1 are emphasized in particular. On the other hand it is shown how the memories in the memory layer M.sub.1 may be directly connected to the underlying processor layer P.sub.1 via buses 7, the stacked configuration allowing such buses 7 to be provided in a large number by being realized as vertical conducting structures, while the configuration layer-on-layer allows for a large number of such bus connections being provided between the processor layer P.sub.1 and the memory layer M.sub.1 and in addition with short signal paths. It will be realized that the juxtaposed arrangement in a surface would in contrast require longer connections and consequently longer transfer times.

Further, the data-processing device as shown comprises combined memory and processor layers MP.sub.1, MP.sub.2, MP.sub.3 provided with processors that are connected mutually and to the processor interface 3 via the same processor bus 4. All the combines memory and processor layers MP comprises one or more processors 5 and one or more RAMs 6. Above the combined memory and processor layers MP there is provided a memory interface 1 with an I/O interface 9 to external units and above the memory interface 1 follows memory layers M.sub.2, M.sub.3, . . . in as large number as desirable and possibly realized as the mass memory of the data-processing device. These memory layers, M.sub.2, M.sub.3, etc. are in their turn connected to the memory interface 1 via memory buses realized as vertical conducting structures 2 through the layers M.sub.2, M.sub.3, . . . .

The integrated data-processing device has a scalable architecture, such that, in principle, the device can be configured with an almost unlimited processor and memory capacity. In particular, the data-processing device can be implemented in various forms of scalable parallel architectures integrated with optimal interconnectivity in three dimensions.

In addition to comprising random accessible memories, the storage unit of the data-processing device can also comprise memories in the form of ROM, WORM or REWRITEABLE or combinations thereof.

The present invention particularly discloses how the three-dimensional scalable single- and multilayer memory and data-processing modules may be implemented with architectures and processing methods making them suitable for application in a scalable integrated data-processing device of the above-mentioned kind, but not necessarily limited thereto.

BACKGROUND OF THE INVENTION

Advanced DRAM demonstration dies are presently available in 1-gigabit (Gbit) modules based on a 0.18 .mu.m process over a 570 mm.sup.2 chip area. The conventional one-transistor DRAM cell requires roughly 10.lambda..sup.2 area (where .lambda. is the minimum feature size) although processing "tricks" can reduce this significantly (40%). However row and column decode, drivers, sense amplifiers, and error correction logic cannot share the same silicon area and account for a significant fraction of the DRAM die area. More importantly, existing DRAM designs to date have not proven scalable to a 3D stacked architecture. By their design, high density DRAM's are also inappropriate as ROM memories. The conventional NOR-gate based ROM requires a nominal cell of 70.lambda..sup.2 (though again reduced by processing tricks) limiting densities to <10.sup.8 bits/cm.sup.2 under even the most aggressive lithography assumptions. Higher densities can only be achieved through the use of both dense metal designs (minimum metal pitch) coupled with 3D integration. Technically and commercially viable devices of this type have as yet not been forthcoming, although the enormous commercial potential has prompted a great deal of R&D efforts by the electronics industry, which in term has spawned a voluminous patent literature.

3D Data Storage

Stacking of thin layers of memory on top of each other to achieve high volumetric and areal densities has been attempted by using e.g. lift-off techniques for inorganic thin film circuitry. However, the background art has led to designs that have proven too complicated or costly to have a commercial impact. In U.S. Pat. No. 5,375,085 "Three dimensional ferroelectric integrated circuit without insulation layer between memory layers", B. E. Gnade et al. have disclosed a layered, passively addressed memory stack based on a ferroelectric memory substance. However, no concrete information is given, in particular relating to processability in multiple levels, showing how complete memory devices can be made that include all the required ancillary active circuitry. Several patent applications involving stacking of thin film memory layers etc. and which are of relevance for the present invention, have been filed by the present applicant. These include Norwegian patent applications NO 973993, NO 980781, the above-mentioned NO 982518, NO 980602 and NO 990867.

Dense Metal Designs

Passive matrix addressing provides a density corresponding to a unit cell area of approximately 4.lambda..sup.2.

A number of patents exist where ROM devices employ passive matrix addressing schemes, e.g.: U.S. Pat. No. 4,099,260 of D. N. Lynes et al.: "Bipolar read-only-memory unit having self-isolating bit-lines"; U.S. Pat. No. 4,400,713 of K. G. Bauge and P. B. Mollier: "Matrix array of semiconducting elements"; U.S. Pat. No. 5,170,227 of M. Kaneko and K. Noguchi: "Mask ROM having monocrystalline silicon conductors"; U.S. Pat. No. 5,464,989 of S. Mori et al.: "Mask ROM using tunnel current detection to store data and a method of manufacturing thereof"; U.S. Pat. No. 5,811,337 by J. Wen: "Method of fabricating a semiconductor read-only memory device for permanent storage of multilevel coded data" and PCT Pat. WO 96/41381 of F. Gonzalez et al.: "A stack/trench diode for use with a multistate material in a non-volatile memory cell". However, such schemes rely explicitly on traditional silicon wafer processing, involving e.g. thermal treatment, implantation and etching procedures which are incompatible with the goals of the present invention, i.e.: low cost and optionally multilevel data storage.

The above-mentioned cited U.S. Pat. No. 5,375,085 discloses devices based on passive matrix addressing, but restricted to the special case of ferroelectric memory materials. The ferroelectric materials referred as examples in that patent have, however, proven unsuitable in simple passive matrix addressed memory schemes due to loss of polarization in unselected cells subjected to repeated partial switching. One- and two-transistor ferroelectric RAM (FERAM) devices avoid this problem, but have not lent themselves to simple 3D scaling.

In U.S. Pat. No. 5,441,907 "Process for manufacturing a plug-diode mask ROM", H-C. Sung and L. Chen discloses a passive matrix addressed ROM where binary data are coded at each matrix crossing point by the presence or absence of a diode connection. However, methods describing fabrication of devices according to the referred patent involve several high temperature steps, include final annealing, which precludes construction of multilayers and the use of low-cost, low temperature compatible materials.

Thin Film ROM Devices

In GB Patent 2,066.566 "Amorphous diode and ROM or EEPROM device utilizing same", S. H. Holmberg and R. A. Flasck discloses thin film memory devices based on fluorine-containing amorphous silicon. In U.S. Pat. No. 5,272,370 "Thin-film ROM devices and their manufacture", I. D. French discloses a ROM device based on thin-film memory cells in a passive matrix addressing arrangement. Emphasis is explicitly on multilevel (i.e. multi-bit) data storage in each memory cell, by providing multilayer structures that can be individually selected for each memory cell.

It is a main object of the present invention to provide architectures and technical solutions where dense bit cell patterns in 2D can be incorporated into 3D storage structures, employing easily implementable, low-cost manufacturing technologies.

It is a further object of the present invention to provide ROM, WORM, and REWRITABLE memory devices with short random access times, high data transfer rates and low power consumption. In the present document, the term "REWRITABLE" shall be used in connection with memory cells where information that has been stored can be exchanged by new information through an erase/write or direct overwrite operation. Depending on the application, this operation may be performed only once, or repeatedly.

It is yet a further object of the present invention to provide integrated data storage and processing devices where memory structures and device architectures can be created in very dense structures characterized by short, highly parallelized interconnection paths in two and three dimensions.

Finally, it is also an object of the invention to provide a fabrication method for a data storage and data-processing apparatus based on low-temperature compatible processes and materials suited therefor.

The above-mentioned objects and advantages are realized by one or more embodiments of the present invention. The objects of the present invention are particularly achieved by exploiting novel materials and processes that make possible the creation of devices with new architectures in two and three dimensions. Salient features in that connection are:

1) Memory modules are made by low-temperature compatible processes and materials i.e. polymers or low temperature processing of poly- or micro- or amorphous silicon. Low-temperature compatible in this context refers to processes not exceeding static temperatures compatible with polymer-like substrates, or transient heating processes limited to times sufficiently short to be similarly compatible. As an example: In laser crystallization of thin film silicon, the temperature in the outermost layer is in fact quite high, but due to the short thermal pulse and total energy density, heat redistributes quickly into supporting layers. Beyond a certain depth, the latter do not reach high temperatures due to calorimetric effects. For simplicity, low temperature compatible processes and materials as described above may be referred to in the following as "low temperature processing" and "low temperature materials".

2) Low temperature processing makes possible the creation of memory modules in one superlayer or a stack of superlayers without damaging underlying circuitry nor other memory layers in the stack. This applies both to devices based on traditional single crystal silicon substrates, as well as plastic substrates with thin-film active circuitry. (In the latter case, the short duration of the heat pulse typically used in laser recrystallization appears to prevent damage to the plastic even at temperatures where a sustained thermal load would cause damage).

3) From 1) and 2) follow a number of beneficial consequences:

Possibility of stacked layers. Leads to:

High volumetric data density, and:

High density, short vertical interconnects, leading to high data throughput:

Low capacitive and resistive interconnects due to short distance

high degree of parallelism (many vertical connections) for large word widths.

Exploiting areas in sublayer single crystal or high performance polycrystalline, amorphous or microcrystalline layer underneath memory modules for tasks requiring high-speed active circuitry. Examples:

Integrated SRAM data cache

Driver and interface electronics

On-board error detection and correction block-oriented circuitry to increase reliability of memory layers

High area data density in each layer due to the passive matrix addressing, with the option of locating driver circuitry layers below and/or above as well as in the same layer.

Vertical interconnections can take many forms: One is penetrating conductors through vias, in which case the short distances and large areas available in the stacked concept permit high data transfer speeds as mentioned above as well as flexible architectures, involving, e.g. staggered arrangement of vias as described in more detail in connection with a preferred embodiment below. Vertical interconnections can also be achieved by electrical conductors in each layer leading to the edge of the layer in question, where they are exposed and can be electrically connected to similarly exposed conductors in other layers. This may e.g. be facilitated by a step-wise extension of the edges of the lower-lying layers. Another class of vertical interconnections relies on contact-less (non-galvanic) communication through the layers. This is possible due to the layered architectures, i.e. capacitive, inductive or optical coupling between circuits in different layers.

A preferred design according to the invention is realized as a layered structure built on a single crystal silicon substrate which contains all active electronic circuitry. The latter communicates with one or more overlying memory layers through vias. Each memory layer contains low-temperature processed diode ROM and/or WORM and/or REWRITABLE arrays where high areal bit density is achieved through the use of passive matrix addressing. Each memory layer constitutes a self-contained entity and requires no high-temperature or chemically aggressive processing that can damage the underlying structures during manufacture. Thus, the memory modules can be positioned on top of active electronic circuitry in the substrate, conserving substrate real estate and providing short electronic pathways between the active circuitry and the memory modules. Furthermore, memory capacity can be expanded by adding more memory layers on top of the first, leading to a 3D stacked structure with very high volumetric bit density.

Devices as described above lend themselves well to "back-end" processing of the memory modules, where all circuitry on the single crystal silicon substrate is first prepared using traditional silicon foundry processing. The subsequent deposition of the memory layer(s) may be performed in a separate facility, e.g. if it is desirable to employ materials and processes in this step which might represent a contamination problem for the silicon processing.

The driver and sense circuits are preferably fabricated in a standard CMOS process on single crystal silicon substrate to minimize costs and to achieve required high data transfer rates. The ROM/WORM/REWRITABLE arrays are then built above the final metallization layer coupled by vias to the underlying drivers. The diodes can be inorganic, e.g. amorphous, polycrystalline or microcrystalline silicon, or they can be based on an organic material such as a conjugated polymer or oligomer. The passive matrix addressing scheme and the 3D architecture employing the low temperature diodes provide a dramatic storage enhancement over all existing ROM/WORM/REWRITABLE designs, at only marginal cost above the underlying CMOS circuit.

For clarity and concreteness, a detailed description of the invention shall be given below in terms of a preferred embodiment based on low-temperature processed poly-Si diode ROM arrays in a stack with four double-layer. The design can be easily extended for WORM memories applications utilizing either induced explosive crystallization of amorphous diodes or conductance modulation of interlayer organic films, and to REWRITABLE memories by incorporating highly functional memory materials in the memory matrices; cf. other patent applications belonging to the present applicant, quoted in the present document.

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description refers to the appended drawing figures, of which

FIG. 1 shows an embodiment of a scalable integrated data-processing device to which the present invention may be applied,

FIG. 2 the schematic layout for a 1 GB ROM apparatus according to an embodiment of the present invention,

FIG. 3 the layout of the row/column addressing lines of a pair of memory planes of the ROM in FIG. 2,

FIG. 4 a staggered stacking arrangement of memory planes of the ROM in FIG. 2,

FIG. 5 a combination of several staggered stacking arrangements of the kind shown in FIG. 4 into a multisegmented staggered stacking arrangement of the memory planes of the ROM in FIG. 2,

FIG. 6 staggered vertical or horizontal vias for connecting through or across memory planes and connecting the latter to underlying circuitry,

FIG. 7 a graph of the access time versus the number of memory block segments,

FIG. 8 a graph of the average addressing power requirement versus the average block (read) addressing size,

FIG. 9 vertical diodes in "on" and "off" memory element in a ROM, and

FIG. 10 vertical diodes as in FIG. 9, but fabricated by a self-aligning and -planarizing process.

DETAILED DESCRIPTION

The schematic layer layout for a 1 gigabyte (GB) apparatus according to an embodiment of the invention is shown in FIG. 2. Row demultiplexers and drivers, sense amplifiers, and column multiplexers are implemented in a conventional VLSI COMO single crystal chip forming the base of the structure. All of the diode-ROM layers are fabricated after completion of the VLSI circuitry above a final dielectric deposition and CMP planarization.

The details of the VLSI CMOS circuitry will not be discussed except as it specifically relates to the memory planes. The drivers and sense amplifiers are essentially identical to those used in conventional DRAM modules and the designs can be lifted almost intact. Row driver inverters will have to be resized to accommodate the high capacitance of the diode-ROM configuration, and the sense amplifiers will need to be modified for slower charging rates.

The memory planes are stacked layerwise and each ROM layer includes simple row/column line crossing linked potentially by a vertical diode structure; a binary 0 (or 1) indicated by the presence of the diode. A total of eight memory planes, each incorporating 10.sup.9 bits, are required to yield the gigabyte module. To reduce the total number of mask levels, row lines are shared between two memory planes--reducing the speed, but simplifying the overall fabrication.

The electrical schematic for each pair of memory planes is shown in FIG. 3. Once a row address is latched (RAS), a final inverter drives one row line to ground. Current flows through the diodes from the column lines (symmetrically from