For the tradeoffs between a lower consumption power of a microprocessor and its process speed, a plurality of clocks and power supply voltages are supplied to each of functional units 104 to 107 and a clock switching circuit and a power switching circuit are provided in each of the functional units. When a program mainly using a particular functional unit, e.g., FPU 106, is executed, the operation speed of FPU 106 is raised more than that in a normal operation mode. To this end, a consumption power control circuit 102 supplies a power/clock switching signal 113c to FPU 106. This power/clock switching signal 113c instructs to raise the clock frequency and power supply voltage to be used by FPU 106. In order to compensate for an increase in the consumption power to be caused by the high speed operation of FPU 106, the consumption power control circuit 102 also supplies a power/clock signal 113b to another functional unit, e.g., CPU 105. This power/clock switching signal 113c instructs to lower the clock frequency of CPU 105.
A method and an apparatus are provided for saving power in a microprocessor. The microprocessor has at least one functional unit, which has a plurality of blocks. The blocks each include a plurality of sub-blocks. It is determined whether there is any instruction for the functional unit. Upon a determination that there is no instruction for the functional unit, the functional unit is shut down. Upon a determination that there is at least one instruction for the functional unit, at least one inactive block of the functional unit is shut down based on the instruction.
In one form, a method for communicating among subsystems coupled to a bus of a computer system on an integrated circuitry chip includes operating subsystems at independent clock frequencies when the subsystems are not communicating with one another on the bus. Selected pairs of the subsystems are operated at a shared clock frequency by selectively varying frequencies of clock signals to the subsystems, so that communication can occur at the shared clock frequency on the bus between the selected subsystems, but at different clock frequencies for respective different pairings of the subsystems, and so that the subsystems can operate at independent clock frequencies when not communicating with other ones of the subsystems. Communication among the subsystems is by a bus-based protocol, according to which when a subsystem is granted access to the bus the subsystem has exclusive use of the bus.
A semiconductor device having a functional circuit block with predictive power controller is provided so as to construct a system LSI manufactured in a practicable number of design steps, which is extensible and in which power is reduced. The functional circuit block includes a prediction circuit and a predictive power shutdown circuit having a power status control circuit. The prediction circuit controls a power status of the functional circuit block by using the power status control circuit, based on input information thereto. When no information is inputted for a predetermined a period of time, the power status control circuit shifts from a power status of the functional circuit block to a low-power status.
An information processing apparatus for autonomously controlling the supply of electric power to each functional unit constituting said apparatus includes a management part for controlling the supply of electric power to each functional unit; an execution control part for issuing an instruction concerning an operation, if the operation is required in the self apparatus; and an instruction recording part for recording an instruction issued by said execution control part; wherein said management part stops the supply of electric power to said execution control part and starts the supply of electric power to said functional unit concerning the instruction issued by said execution control part, if said execution control part ends issuing the instruction, whereby said functional unit executes the instruction recorded in said instruction recording part.
