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BACKGROUND OF THE INVENTION
The present invention relates to a motor control device for three-phase
brushless DC motors used in assist motors in electric power steering
devices. More specifically, the present invention relates to a motor
control device that sets a dead time value actively so that dead time is
minimized in order to improve the motor's power supply usage efficiency,
the controllability, and to reduce noise.
Three-phase brushless motors (hereinafter referred to as motors) with U-,
V-, and W-phases that are easy to control and provide high torque
relatively quickly are used, e.g., as assist motors in electric power
steering devices. A control device for this type of motor is equipped with
a transistor inverter having switching means formed from power MOSFETs
(Metal Oxide Semiconductor Field Effect Transistor) in a motor drive
device. This motor drive device is formed with high-level and low-stage
FETs for each of the U-, V-, and W- phases. The FETs are switched on in an
alternating manner by the motor control device, which is equipped with a
CPU, thus improving power supply usage efficiency and also providing
smooth drive. However, if both a high-level FET and a low-stage FET are on
at the same time for some reason, a through current flows through the
high-level FET and the low-stage FET for that phase without flowing
through the motor, resulting in a circuit that goes directly from the
power supply to a ground GRD. Since the current does not pass through the
coils of the motor, which have a high resistance, the resistance is low
and the current is high, leading to damage to the FETs. Therefore, when a
FET is to be turned on, a delay circuit is used to provide dead time so
that a predetermined time elapses after the other FET is turned off before
the FET is turned on, thus protecting the FETs.
However, two similar power MOSFETs can have varying characteristics. The
differing characteristics can be response time and signal rise time and
the like. To take all possibilities into account by providing leeway with
a high dead time results in reduced power supply usage efficiency as well
as contributing to non-linearity in the motor drive signal, which can lead
to torque ripple that makes operation difficult and noise.
Dead time correction is one approach to correcting non-linearity caused by
dead time. Although this involves complex operations, the processing is
static and therefore cannot respond appropriately to changes over time and
temperature changes.
OBJECTS AND SUMMARY OF THE INVENTION
In order to overcome these problems, the object of the present invention is
to provide a motor control device that allows quick discovery of
through-current during dead time even if, besides static tolerances such
as production variations between switching means, there are differences
caused by dynamic changes such as temperature changes and changes over
time. Another object of the present invention is to provide a motor
control device in which dead time is set in an active manner to minimize
dead time and non-linearity caused by variations in switching means
characteristics are minimized to improve motor efficiency and
responsiveness while reducing noise.
A motor control device according to claim 1 includes: high-stage FETs
disposed on a power-supply side and low-stage FETs disposed on a ground
side, the FETs being switching means connected in series in circuits
disposed between an application point of a power supply and a ground point
and associated with U-, V-, and W-phases of a brushless DC motor, the FETs
being selected in an exclusive manner; connection points disposed between
the high-level FETs and the low-stage FETs supplying drive currents to U-,
V-, and W-phase motor coils based on combinations of open/close states of
the high-level FETs and the low-stage FETs for each phase; current
detecting means detecting currents in the circuits; and switch controlling
means controlling switching means and driving the brushless DC motor.
Means for detecting irregular current detecting current at a predetermined
timing using current detecting means. Means for evaluating motor drive
circuit irregularities evaluates motor drive circuit irregularities based
on current values detected by irregular current detecting means.
In a motor control device according to this structure, irregularities in
the motor drive circuit are detected immediately by motor drive circuit
irregularity evaluating means based on the current value detected by
irregular current detecting means.
In addition to the structure of the motor control device described in claim
1, the motor control device according to claim 2 also includes correcting
means correcting a dead time setting based on a current value detected by
irregular current detecting means.
In addition to the operations provided by the motor control device
described in claim 1, this motor control device uses correcting means to
correct dead time settings based on a current value detected by irregular
current detecting means when motor drive circuit irregularity evaluating
means detects and irregularity.
In addition to the structure of the motor control device described in claim
1, in the motor control device according to claim 3, irregular current
detecting means detects a trailing edge when a gate signal for the U-, V-,
or W-phase goes from on to off or a leading edge going from off to on and
detects through-current during a dead time for each phase with current
detecting means using this timing as a reference.
In addition to the operations provided by the motor control device
described in claim 1, this motor control device detects a trailing edge
when a gate signal for the U-, V-, or W-phase goes from on to off or a
leading edge going from off to on. Through-current is checked at a timing
appropriate for each phase, thus allowing precise control.
In addition to the structure of the motor control device described in claim
1, in the motor control device according to claim 4, current detecting
means is disposed so that current flowing through the low-stage FETs is
detected. Irregular current detecting means detects when controlling means
is sending "on" gate signals to U-, V-, and W-phase high-stage FETs while
sending "off" gate signals to all low-stage FETs and detects
through-current in the phases at this timing using current detecting
means.
In addition to the operations provided by the motor control device
described in claim 1, this motor control device checks for through-current
when U-, V-, W-phase low-stage FET gate signals are all off. Thus,
irregularities can be detected by performing current detection on just one
position, allowing a simple structure.
In addition to the structure of the motor control device described in claim
1, in the motor control device according to claim 5, current detecting
means is disposed so that current flowing through the low-stage FETs is
detected. Irregular current detecting means detects when controlling means
is sending "on" gate signals to U-, V-, and W-phase low-stage FETs while
sending "off" gate signals to all high-stage FETs and detects
through-current in the phases at this timing using current detecting
means.
In addition to the operations provided by the motor control device
described in claim 1, this motor control device checks for through-current
when U-, V-, W-phase high-stage FET gate signals are all off. Thus,
irregularities can be detected by performing current detection on just one
position, allowing a simple structure.
In addition to the structure of the motor control device described in claim
2 or claim 3, in the motor control device according to claim 6 correcting
means reduces by a predetermined amount a dead time setting set up based
on a turn-off dead time and a turn-on dead time set up ahead of time if a
predetermined through-current is not detected by irregular current
detecting means. If the predetermined through-current is detected, the
correcting means increases the dead time by a predetermined amount.
In addition to the operations provided by the motor control device
described in claim 2 or claim 3, this motor control device can reduce dead
time if no through-current is flowing. This allows power supply usage to
be improved and torque ripple and noise to be reduced. If through-current
is flowing, the turn-off dead time and the turn-on dead time are reset to
extend the dead time so that the FETs can be safely protected.
In addition to the structure of the motor control device described in claim
6, in the motor control device according to claim 7, if the through
current is detected at a predetermined dead time value, correcting means
does not reduce the dead time below the dead time value at which the
through-current was detected.
In addition to the operations provided by the motor control device
described in claim 6, when a through-current is detected at a
predetermined dead time setting, correcting means does not reduce the
setting below the dead time setting at which the through-current was
detected. This safely protects the FETs.
In addition to the structure of the motor control device described in claim
6 or claim 7, in the motor control device according to claim 8 controlling
means sets dead time values independently for each of the phases.
In addition to the operations provided by the motor control device
described in claim 6 or claim 7, dead time is set independently for each
phase. Thus, optimal settings that correspond to variations in individual
FETs can be provided.
In addition to the structure of the motor control device described in any
one of claim 6 through claim 8, in the motor control device according to
claim 9, correcting means sets the dead time setting value independently
of turn-off dead time and turn-on dead time.
In addition to the operations provided by the motor control device
described in any one of claim 6 through claim 8, the dead time is set
independently for the turn-off dead time and the turn-on dead time. Thus,
optimal settings corresponding to variations in individual FETs can be
provided.
The above, and other objects, features and advantages of the present
invention will become apparent from the following description read in
conjunction with the accompanying drawings, in which like reference
numerals designate the same elements.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified drawing of an electric power steering device.
FIG. 2 is a detailed drawing of a motor control device 20 shown in FIG. 1.
FIG. 3 is a control block diagram showing functions executed by a program
in a CPU 21.
FIG. 4 is a timing chart illustrating the timing at which a CPU 21 switches
U-, V-, W-phase high-level FETs and low-stage FETs.
FIG. 5 is a detailed drawing of an amplifier circuit.
FIG. 6 is a flowchart showing a procedure for evaluating motor drive
circuit irregularities performed by a CPU 21.
FIG. 7 is a flowchart showing a procedure for dead time active control
performed by a CPU 21 serving as correcting means of a second embodiment.
FIG. 8 is a flowchart showing a procedure for dead time active control
performed by a CPU 21 serving as correcting means of a third embodiment.
[List of designators]
B: power supply;
GRD: ground;
P: application point;
Q, 83U, 83V, 83W: connection point;
AU, AV, AW: operational amplifier;
RU, RV, RW: shunt resistor;
t1, t2, tu, tv, tw: timing;
td: dead time;
DT: dead time;
DTmin: minimum dead time setting;
Id, Ie, I.sub.0 : current value;
Iu, Iv, Iw: current;
6: motor;
20: motor control device;
21: CPU;
24: motor drive device serving as motor drive circuit;
81U, 81V, 81W: high-level FET serving as switching means;
82U, 82V, 82W: low-stage FET serving as switching means
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
(First Embodiment)
Referring to FIG. 1 through FIG. 6, a first embodiment of the present
invention will be described in the form of a motor control device 20 in an
electric power steering device. The motor control device 20 is equipped
with motor drive circuit irregularity evaluating means.
FIG. 1 shows a simplified drawing of an electric power steering device. A
torsion bar 3 is disposed on a steering shaft 2 connected to a steering
wheel 1. This torsion bar 3 is equipped with a torque sensor 4. When the
steering shaft 2 is turned and force is applied to the torsion bar 3, the
torsion bar 3 is twisted in response to the applied force. This twisting,
i.e., a steering torque .tau. applied to the steering wheel 1, is detected
by the torque sensor 4.
A reduction gear 5 is secured to the steering shaft 2. This reduction gear
5 is meshed against a gear 7 attached to the rotation shaft of a brushless
DC motor (hereinafter referred to as a motor 6), which serves as the
electric motor. This motor 6 is formed as a three-phase synchronous
permanent magnet motor.
A rotation angle sensor 30 formed with an encoder for detecting the
rotation angle of the motor 6 is disposed on the motor 6 (see FIG. 3). The
rotation angle sensor outputs a zero phase pulse series signal that is
shifted .pi./2 from the rotation of the rotor of the motor 6 and a
zero-phase pulse series signal representing the reference rotation
position.
A pinion shaft 8 is secured to the reduction gear 5. The end of the pinion
shaft 8 is secured to a pinion 9, and this pinion 9 meshes with a rack 10.
Tie rods 12 are secured to the ends of the rack 10, and knuckles 13 are
rotatably connected to the ends of the tie rods 12. Front wheels 14, in
the form of tires, are secured to the knuckles 13. Also, one end of the
knuckle 13 is rotatably connected to the cross member 15.
Thus, when the motor 6 rotates, the number of rotations is reduced by the
reduction gear 5 and transferred to the pinion shaft 8. The rotation is
then transferred to the rack 10 by way of the pinion and the rack
mechanism 11. Then, the rack 10 can use the tie rod 12 to change the
direction of the vehicle by changing the orientation of the front wheels
14 disposed on the knuckles 13.
A car speed sensor 16 is disposed on the front wheel 14. This car speed
sensor 16 sends the current car speed to a CPU 21 in the motor control
device 20 by way of an interface. This is done by sending a pulse signal
having a period corresponding to the rotation count of the front wheel 14.
Also, the torque sensor 4 sends a voltage corresponding to the steering
torque .tau. of the steering wheel 1 to the CPU 21 by way of an interface.
The motor control device 20 controls the motor 6 by sending it a drive
signal based on signals from the car speed sensor 16 and the torque sensor
4.
Next, the electronic structure of the motor control device 20 will be
described. The motor control device 20 is equipped with: the CPU 21, a ROM
22, a RAM 23, and a motor drive device 24 including a power supply
supplying drive current to U-, V-, and W-phases, an inverter, and
switching means. This motor control device 20 corresponds to switch
controlling means of the present invention. The ROM 22 stores a control
program for having the CPU 21 perform calculation operations, data needed
for calculations, and the like. Also, a basic assist map is also stored in
the ROM 21. The basic assist map corresponds to the steering torque .tau.
(rotation torque) and is used to determine a basic assist current
corresponding to a car speed. The basic assist map stores basic assist
currents associated with steering torques .tau.. The RAM 23 temporarily
stores the calculation results from calculation operations performed by
the CPU 21, measurement values, a dead time DT determined from a turn-off
dead time and a turn-on dead time, a dead time minimum value DTmin, and
the like. In this embodiment, the ROM 21 is formed from writable storing
means, e.g., an EEPROM. This allows the dead time DT and the dead time
minimum value DTmin to be saved even if the power is turned off.
FIG. 2 is a detailed drawing of the motor control device 20 shown in FIG.
1. The motor control device 20 will be described in further detail. The
main elements of the motor control device 20 are the CPU 21, which
performs calculations, and the motor drive device 24, which supplies power
to the motor 6.
The motor drive device 24 is formed from the sections of FIG. 2 excluding
the CPU21, the ROM 22, and the RAM 23 of the motor control device 20. As
shown in FIG. 2, the motor drive device 24 includes a transistor inverter
formed from power MOSFET (Metal Oxide Semiconductor Field Effect
Transistor) serving as switching means. Parasitic diodes are generated in
these FETs. These diodes function as flywheel diodes that absorb
counterelectromotive force connected in parallel to coils. The series
circuit of the FET 81U and the FET 82U, which corresponds to the U phase,
the series circuit of the FET 81W and the FET 82W, which corresponds to
the V phase, and the series circuit of the FET 81W and the FET 82W, which
corresponds to the W phase, are connected in parallel.
The voltage from a power supply B, in the form of a DC12V battery mounted
in the vehicle, is applied to a drain-side point P of the FET 81U, the FET
81V, and the FET 81W of the series circuits. The source terminals of the
FET 82U, the FET 82V, and the FET 82W come together at connection point Q
which is connected to a ground GRD.
In this embodiment, the U-phase, V-phase, and W-phase power-supply side FET
81U, FET 81V, and FET 81W are referred to as "upper-stage FETs". The
ground-side FET 82U, FET 82W, and FET 82W are referred to as "lower-stage
FETs".
A connection point 83U between the FET 81U and the FET 82U is connected to
a U-phase coil of the motor 6. A connection point 83V between the FET 81V
and the FET 82V is connected to a V-phase coil of the motor 6. A
connection point 83W between the FET 81W and the FET 82W is connected to a
W-phase coil of the motor 6.
Shunt resistors RU, RV, and RW are respectively inserted between the FET
82U, the FET 82V, and the FET 82W of the lower-stage FETs and the
connection point Q connected to the ground GRD. Differential input
terminals of operational amps AU, AV, AW are connected to the terminals of
the shunt resistors RU, RV, RW. The power-supply sides of the shunt
resistors RU, RV, RW are connected to the noninverted input terminals of
the operational amps AU, AV, AW, and the ground sides of the shunt
resistors RU, RV, RW are connected to the inverted input terminals of the
operational amps AU, AV, AW respectively. The shunt resistors RU, RV, RW
have very small resistances that do not affect motor drive. Thus, when
current flows through the shunt resistors RU, RV, RW, a slight potential
difference is generated between the terminals. These potential differences
are amplified by the operational amps AU, AV, AW respectively, and these
are digitized by A/D converters 86U, 86V, 86W. Based on this, the CPU 21
calculates the currents flowing through the shunt resistors RU, RV, RW.
FIG. 5 shows a detailed drawing of an amplifier circuit. The same amplifier
circuit is used for each phase, so the U-phase circuit will be described
here. In this amplifier circuit, a differential amplifier is formed using
the differential input type operational amp AU. Since current flows
bi-directionally in all phases, the amplifier circuit is supplied with
+2.5 volts to serve as a reference voltage V1 via a resistor R2. A
power-supply side V0 of the U-phase circuit shunt resistor RU is connected
to the noninverted input terminal + operational amp AU via a resistor R1.
Also, the ground GRD of the shunt resistor RU is connected to the inverted
input terminal - of the operational amp via a resistor R3. Also, a
negative feedback resistor R4 is connected to the inverted input terminal
- and the output terminal. In this circuit, R1=R3 and R2=R4. Thus, the
amplification factor G is determined by R4/R3. These are formed as "shunt
ammeters", and correspond to current detecting means of the present
invention.
The shunt resistors RU, RV, RW of current detecting means do not have to be
disposed between the lower-stage FETs and the ground GRD. The design can
be modified so that the shunt resistors are disposed between the
upper-stage FETs and the power-supply B or the like. Furthermore, current
detecting means does not have to be formed from a shunt ammeter. Another
structure can be used as long as it can directly or indirectly detect
current.
The CPU 21 is connected via a high-stage drive circuit 87 to the gates of
the FET 81U, the FET 81V, and the FET 81W, i.e., the upper-stage FETs.
Also, PWM control signals UU, VU, WU (the PWM control signal for a phase
includes a PWM wave signal and a signal indicating the rotation direction
for the motor 6) are received from the CPU 21.
The motor drive device 24, formed as a transistor inverter, generates
three-phase excitation currents corresponding to the PWM control signals
UU, VU, WU, and these are sent to the motor 6 via a three-phase excitation
current path.
FIG. 4 shows a timing chart illustrating the timing of gate signals, which
are control signals from the CPU 21 for the switching of the U-, V-, and
W-phase high-stage and low-stage FRTs. As shown at the top of FIG. 4, a
triangular wave PW is generated to serve as the PWM period. Switching
timing is determined based on threshold levels corresponding to the
U-phase, the V-phase, and the W-phase. More specifically, when the
triangular wave PW reaches a phase threshold level, switching takes place
from high-stage FET to low-stage FET. Also, if a value drops below a
threshold level, switching takes place back from low-stage FET to
high-stage FET.
If the high-stage FET and the low-stage FET for the same phase are on at
the same time, a "through-current" flows directly from the power supply B
through the high-stage FET and the low-stage FET for the phase to the
ground GRD without passing through the motor 6. Since the current does not
pass through the high-resistance coils of the motor 6, the resistance of
the circuit is low and a high current can flow. This can lead to damage to
the high-stage FET and the low-stage FET. Therefore, to prevent
through-currents, a dead time td is provided in the timing of the
low-stage FET 82W using a delay circuit.
Even if there is no gate signal from the CPU 21, a through-current can also
take place if there is poor insulation due to a malfunction in an FET. In
these cases, unlike bad dead time settings, a very small current may flow
during the initial stage of the malfunction. Since this can also lead to
further malfunctions, e.g., in other FETs, as well as significant control
failures, the problem must be discovered and corrected quickly.
The timing chart in FIG. 4 shows the control on/off signals (gate signals)
for the upper-stage drive circuit 87 or the lower-stage drive circuit 88.
The actions of the drive circuit 88 and the FETs are delayed by switching
delays from the gate signals. The turn-off dead time td.sub.off indicated
here refers to the interval between when one of the FETs is turned off by
a gate signal and when the current flowing through the FET is turned off.
This time is the beginning of dead time. The turn-on dead time td.sub.on
refers to the interval between when one of the FETs is turned on by a gate
signal and when current through the FET is turned on. This time marks the
end of dead time. Both of these are triggered by the gate signal. Thus,
the dead time td would, theoretically, be the sum of the turn-off dead
time td.sub.off and the turn-on dead time td.sub.on. However, there can be
various types of variations that affect the actual dead time td, so gate
signal timings are set up with a margin in addition to these time lags.
Thus, the dead time td must be an interval that provides a predetermined
amount of leeway rather than simply providing non-overlapping intervals.
This predetermined dead time td can vary depending on the switching delay
status and can also change. More specifically, the time can change
depending on the characteristics of the FET itself, variations between
parts, temperature changes, changes over time, the effect of noise, and
the like. Therefore, in order to be safe and avoid through-current through
the FETs of all phases, the conventional technology used uniform
fixed-interval with adequate margins for turn-off dead time td.sub.off and
turn-on dead time td.sub.on settings. While the dead time td is a
necessary and unavoidable interval, including a margin that is greater
than needed can reduce power supply usage and lead to torque ripple and
noise. Thus, it would be preferable to keep the interval as short as
possible.
The timing at which control signals are sent to the FETs will be described
using FIG. 4. Referring to the top of FIG. 4, at time t0, the initial
state, the triangular wave PW has not reached the threshold levels of U,
V, W. Thus, the high-level FETs are turned on and the low-stage FETs are
turned off. At this point in time, the circuit shown in FIG. 2 going from
the power supply B to the ground GRD is not closed. At this initial
timing, no counterelectromotive force due to inductance of the motor coil
is generated. At time t2, even though this is another valley in the
triangular wave, the motor 6 is rotating. Thus, even if there is no power
being supplied by the power supply B to the motor 6, a switch-off will
result in current flowing due to the counterelectromotive force generated
by the coil of the motor 6.
At this point, current generated by the U-phase coil of the motor, not
shown in the figure, will, for example, split between the V-phase and the
W-phase within the motor 6. The current passing through the V-phase
connection point 83V will flow from the high-level FET 81V to the
connection point P, and the current passing through the W-phase connection
point 83W will flow from the high-level FET 81U to the connection point P.
These currents combine at the connection point P and go from the
high-stage FET 81U of the U phase to the U phase of the motor 6 by way of
the connection point 83U.
In the case of time t2, the current flows through the high-level FETs 81U,
81V, 81W and does not flow through the shunt resistors RU, RV, Rw. Thus,
there is no potential difference between the terminals of the shunt
resistors RU, RV, RW.
Next, when the triangular wave PW goes from tw to a level associated with
the W phase, a control signal WH stops and the high-level W-phase FET 81W
is turned off. Next, after the dead time td elapses, a control signal WL
is sent and the low-stage W-phase FET 82W is turned on. The dead time td
will be described in further detail. When the control signal WH is stopped
according to a pre-set timing, the turn-off dead time td.sub.off triggered
by the high-level W-phase FET 81W. A predetermined margin is provided and
the control signal WL is sent to the FET 82W at a timing calculated ahead
of time based on the turn-on dead time td.sub.on from the W phase
low-stage FET 82W. In this manner, the dead time td is based on the
turn-off dead time td.sub.off determined by when the control signal WH is
sent and the turn-on dead time td.sub.on determined by when the control
signal WL is sent. The timing at which the control signals WH, WL are sent
is determined by data stored in the ROM 22 and the RAM 23 of the CPU 21
using the triangular wave PW as a reference.
When the W-phase low-stage FET 82W i | | |
