An exemplary data processing device includes a clock recovery system for locking a clock frequency to time stamps (PCR) of an incoming data stream, e.g. MPEG. The exemplary device uses a free running clock (20) that generates a reference frequency (FREF) from which a desired locked clock frequency is synthesized (25,35) under control of a processing unit (24,34) that compares (241,341) the locked clock frequency to the time stamps (PCR). MPEG audio and video processing clock frequencies are synthesized (25,35) from a free running reference frequency (FREF) and locked to the MPEG time base on basis of time stamps (PCR) provided in the MPEG data stream. Other sub-systems (23,23') run on frequencies that are not locked to the time base, e.g. simple multiples (22,22') of the free running reference frequency (FREF).
A data recovery circuit has a phase-locked loop for generating a plurality of clock signals; an oversampling unit for non-integer times oversampling serial data, and outputting the oversampled result as sample data formed of a plurality of bits; a pattern detector for receiving the sample data, and generating a pattern signal; a state accumulator for receiving the pattern signal, accumulating the frequency of occurrence of the pattern signal, and outputting the pattern signal having the highest frequency of occurrence as a state signal; a state selector for receiving the state signal, and generating a state selection signal for selecting bits at predetermined positions in the sample data; and a data selector for receiving the sample data, selecting bits of the sample data in response to the state selection signal, and outputting the selected bits as recovered data formed of a plurality of bits.
To provide an integrated information processing unit that is capable of producing images and sounds of high quality. It includes a control unit, information processing units, and a merge unit. Each of the information processing units includes a counter for synchronization purpose. The information processing units performs a predetermined processing based on the measured value obtained by the counter for synchronization purpose. The control unit simultaneously provides a trigger of measurement of synchronization clocks to all counters for synchronization purpose and individually provides a reset signal to the counters for synchronization purpose which the reset signal is for initializing the measured value obtained by the counters for synchronization purpose. The merge unit merges information processed by the information processing units according to the unit of output (in frame) of, for example, a display device.
During decoding and processing of program clock reference (PCR) values in MPEG-2 transport streams, a first initial difference value is obtained by calculating a difference between a first detected PCR value and a system time clock (STC) value generated when the first PCR value is detected. Depending on the update status of the PCR values, a second initial difference value is obtained by calculating a difference between a second detected PCR value and a STC value generated when the second PCR value is detected. Thereafter, a composite difference value is obtained by further calculating a difference between the first initial difference value and the second initial difference value. Subsequently, the first and second initial difference values, and the composite difference values are calculated for a predetermined number of detected PCR values so that the decoder clock signal is generated and maintained at approximately the same frequency as an encoder clock signal.
Devices and methods are disclosed for managing an output of an output stream. One embodiment relates to a method of tracking an output of an A/V decoder. In this embodiment, indication of an output stream time reference and a location of at least one output sample are received. The received time reference is compared to the output sample and the output sample rate of the A/V decoder is adjusted.
A method for synthesizing a clock signal with multiple frequency outputs for use in a converter for converting a non-interlacing scan data into an interlacing scan data is disclosed. The converter provides a first reference clock signal with a frequency F1. The method includes the steps of receiving the first reference clock signal with the frequency F1 to generate and output a clock signal with a frequency F1.times.N, proceeding a divided-by-P1 and a divided-by-P2 operations on the clock signal with a frequency F1.times.N, respectively, to output a first output clock signal with a frequency F1.times.N/P1 and a second output clock signal with a frequency F1.times.N/P2, respectively. The value P2/P1 correlates to a ratio of the pixel number of a horizontal scan line in the non-interlacing scan data to that in the interlacing scan data. In addition, a clock signal synthesizer with multiple frequency outputs is also disclosed.
