A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node .alpha. is raised. When the potential of the node .alpha. reaches (VDD-VthN), the node .alpha. becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFT 105 is further raised due to an operation of a capacitance means 107 as the potential of the output node is raised, so that the potential of the gate electrode of the TFT 105 becomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT 105. An output at the subsequent stage is then inputted to a TFT 103 to turn the TFT 103 On, while the potential of the node .alpha. of TFTs 102 and 106 is dropped to turn the TFT 105 OFF. As a result, the potential of the output node becomes Low level.
A shift register includes, in the output stage, a first transistor connected between an output terminal and a first clock terminal and a second transistor connected between the output terminal and a first power terminal. Third and fourth transistors constitute an inverter which inverses the level of the gate of the second transistor and outputs it to the gate of the first transistor. An isolation circuit formed by fifth and sixth transistors is provided between the gate of the first transistor and the gate of the fourth transistor. The fifth transistor is diode-connected. When the gate of the first transistor becomes higher than the gate of the fourth transistor, the first and fourth transistors are electrically isolated from each other.
It is an object of the invention to provide a semiconductor circuit requiring less number of transistors included in the semiconductor circuit and accurately serving as a shift register without providing a level shifter. The semiconductor circuit includes: an m (m is an arbitrary positive integer, m.gtoreq.3) stage of a circuit group having a p-channel transistor, in which a first terminal is connected to a high potential power source, and an n-channel transistor, in which a first terminal is connected to a low potential power source; and an inverter circuit. A clock signal is input to a gate of the n-channel transistor in the (2n-1)th stage (n is an arbitrary integer, m.gtoreq.2n.gtoreq.2). An inverted clock signal is input to a gate of the n-channel transistor in the 2n-th stage (n is an arbitrary integer, m.gtoreq.2n.gtoreq.2).
A circuit with a large load driving capability, which is structured by single polarity TFTs, is provided. With a capacitor (154) formed between a gate electrode and an output electrode of a TFT (152), the electric potential of the gate electrode of the TFT (152) is increased by a boot strap and normal output with respect to an input signal is obtained without amplitude attenuation of an output signal due to the TFT threshold value. In addition, a capacitor (155) formed between a gate electrode and an output electrode of a TFT (153) compensates for increasing the electric potential of the gate electrode of the TFT (152), and a larger load driving capability is obtained.
A drive circuit of a display device, which comprise only single conductive TFTs and in which amplitude of an output signal is normal, is provided.A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node a rises. When the potential of the node a reaches (VDD-VthN), the node a became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105. An output at the subsequent stage is then inputted to TFTs 102 and 103 to turn the TFTs 102 and 103 ON, while the potential of the node a drops down to turn the TFT 105 OFF. A TFT 106 turns ON at the same time so that the potential of the output node would reach the level L.
When a digital video signal inputted to a latch circuit is Hi electric potential, undesirably a current flows continuously for one horizontal period at maximum, and this causes a great increase in power consumption of a semiconductor device. Therefore an object of the present invention is to provide a display device in which power consumption can be reduced by minimizing occurrence of the current path during the circuit operation, as well as a driving method. The present invention provides a semiconductor device in which two outputs, a non-inverted output and an inverted output, are obtained when a digital video signal is inputted and therefore occurrence of the current path can be minimized in a downstream buffer driven by these signals. Furthermore, a semiconductor device with reduced power consumption is provided by using the structure described above.
