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Description  |
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TECHNICAL FIELD
The present invention relates to a semiconductor memory device and a test
system and, mainly, a technique effective for use in a technique of a
probing test on a dynamic RAM (Random Access Memory).
BACKGROUND ART
An example of a memory integrated circuit capable of realizing the
functions of a timing margin test, a voltage margin test, and detection of
abnormal current by built-in functions is disclosed in the publication of
Japanese Unexamined Patent Application No. Hei 8(1996)-315598. A memory
integrated circuit of the publication has therein a built-in test function
(BIST) unit for generating a memory test signal and various control
signals, a timing generation circuit and a voltage generation circuit
which are controlled by an output signal of the sequence unit, and a
current sensor for detecting an abnormal current, in which a
current-to-voltage converting circuit and an analog-to-digital converting
circuit are connected in series.
In the memory integrated circuit having therein, in addition to the test
built-in function unit, timing generation circuit, a voltage generation
circuit, a current-to-voltage converting circuit, and a current sensor,
the scale of the test circuit occupying the memory integrated circuit is
large; and, moreover, since the test circuit is used only at the time of a
test, there are problems in that the chip size is enlarged, in terms of
storage bits as the inherent function of the memory integrated circuit,
and the current consumption is increased. The publication indicates that
the problems of the circuit scale and the like are solved by a relative
decrease in the test circuit area in association with a finer circuit and
an increase in the capacity of the memory. However, it is not realistic to
allow a large-scale test circuit, as described above, to be built in a
general memory, such as dynamic RAM having storage capacity of about 64
Mbits or 256 Mbits as practically used at present.
The throughput of a probing test on a dynamic RAM or the like is determined
by test time per chip and the number of chips (the number of chips
simultaneous measured). The number of chips simultaneous measured is,
however, under constraints of each of various hardware. For example, the
number of bonding pads of a synchronous DRAM (Dynamic RAM) of 64 Mbits is
equal to at least 60 to 70 which is the sum of about 54 of external
terminals except for NC pins and special pads used for a probing test.
On the other hand, the maximum number of needles of a probe card to be
electrically connected to the bonding pads is about 1,000 to 1,500.
Accordingly, the maximum number of devices to be measured simultaneously
is about 20. When the number of devices to be simultaneously measured
increases, the number of generating times of signals, the number of
comparators, and the number of power units on the tester side are also
increased, thereby raising the price of the tester. Further, it causes
problems such that the cost of a multi-needle probe card increases and the
life becomes shorter. Consequently, it is not easy to increase the number
of devices to be simultaneously measured.
The inventors of the present invention have therefore examined solution of
the problems while minimizing the number of needle pads used for a probing
test. In association with the increase in the diameter of a wafer in
recent years, the number of memory chips obtained is conspicuously
increasing. It is estimated that the number of chips to be simultaneously
measured has to be increased more and more. As methods of decreasing the
number of needle pads at the time of a probing test, reduction in the
number of power source needle pads, reduction in the number of data
input/output pads, reduction in the number of address input pads, and
reduction in the number of clock input pads can be mentioned. The power
source pads can be eliminated by connecting the power source in a memory
chip except for a pair of VCC and VSS as long as the characteristics can
be maintained. If the address input pads and clock input pads are
eliminated, however, tests of reading and writing data from/to a memory by
designating an address cannot be conducted. A method of designating memory
access patterns such as matching patterns by a simple control from the
outside and generating them on the inside may be considered. It is,
however, estimated that the logic in the chip becomes large and
complicated, it causes an increase in chip size and deterioration in
yield, and the method does not contribute to reduction in cost as a total.
An object of the invention is, therefore, to provide a semiconductor memory
device and a test system capable of conducting a memory test with a simple
configuration. Another object of the invention is to provide a
semiconductor memory device and a test system capable of conducting a
probing test with a smaller number of needle pads. Further another object
of the invention is to provide a semiconductor memory device and a test
system capable of simultaneously measuring the increased number of chips.
The above and other objects and novel features of the invention will
become apparent from the description of the specification and the attached
drawings.
DISCLOSURE OF THE INVENTION
A representative technique of the present invention disclosed in the
specification will be briefly described as follows. A memory circuit
having a memory cell array in which a plurality of memory cells are
provided at intersection points of a plurality of word lines and a
plurality of bit line pairs and a peripheral circuit for performing an
operation of selecting an address is provided with: an arithmetic unit
which is also called an arithmetic circuit, a computing unit or a
computing circuit below for generating an address signal for a test on the
memory circuit; a packet decoder for designating the kind of operation on
the arithmetic unit; and an input circuit for supplying a test signal
comprising a plurality of bits for designating a test operation to the
packet decoder.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram related to a test circuit of an example of a
semiconductor memory device according to the invention;
FIG. 2 is a timing chart showing an example of an input protocol of test
signals in the semiconductor memory device according to the invention;
FIG. 3 is a diagram for explaining bit patterns corresponding to the format
A of FIG. 2 and their operations;
FIG. 4 is a diagram of the structure of pads of an SDRAM according to the
invention as an example;
FIG. 5 is a block diagram showing an example of a test circuit mounted on
the SDRAM according to the invention;
FIG. 6 is a circuit diagram showing an example of a packet control PC and a
data input buffer DIB of FIG. 5;
FIG. 7 is a circuit diagram showing an example of a packet decoder PDEC in
FIG. 5;
FIG. 8 is a circuit diagram showing an example of an arithmetic circuit ALU
in FIG. 5;
FIG. 9 is a waveform chart for explaining the operation of the arithmetic
circuit ALU in FIG. 8;
FIG. 10 is a schematic layout sketch showing an example of the SDRAM
according to the invention;
FIG. 11 is a schematic layout sketch showing an example of the SDRAM
according to the invention;
FIG. 12 is a circuit diagram showing a simplified example starting from
address input until data output and mainly illustrating a sense amplifier
of the SDRAM according to the invention;
FIG. 13 is a general block diagram showing an example of the SDRAM
according to the invention; and
FIG. 14 is a schematic sketch for explaining a test system according to the
invention.
BEST MODE FOR CARRYING OUT THE INVENTION
The invention will be described in more detail with reference to the
attached drawings.
FIG. 1 is a block diagram related to a test circuit of an example of a
semiconductor memory device according to the invention. The embodiment is
directed to, although not particularly limited, a synchronous dynamic RAM
(which may be simply called an SDRAM hereinbelow).
An SDRAM core includes peripheral circuits such as a memory array and an
address selection circuit. The SDRAM has, in addition to the above, an X
address latch, a Y address counter, a mode register, a timing generator,
and a vendor test. By controlling the components by a packet decoder and a
pattern generation controlling circuit which construct a test circuit, a
probing test is carried out.
In I/O (input/output) terminals provided in correspondence with the SDRAM
core, four data input/output terminals DQ0 to DQ3 are used as terminals of
input and output signals for test. A pad CKEP used for mode entry in
control signals, a clock terminal CLK, and a chip select terminal CS/ are
used to receive test signals from the terminals DQ0 to DQ3.
Only a pair of a source voltage terminal VCC for supplying a power and an
earth terminal VSS of the circuit are used for a test. A pad VPP (step-up
voltage), a pad VBB (substrate back-bias voltage), and pads VDLP, VDLA,
VPLT, and VBLR (internal step-down voltage) for monitoring an internal
voltage are provided for a probing test. As a result, in the SDRAM of the
embodiment, irrespective of the storage capacity of about 64 Mbits as will
be described hereinlater, the number of electrodes (pads) used for a test
can be decreased to 15.
In the embodiment, test signals of four bits supplied from the data
input/output terminals DQ0 to DQ3 are formed as a packet (packet of
information), and setting of all of operation controls for testing the
SDRAM is realized by a single test signal or a combination of test
signals. The test signal is supplied to a packet decoder where the bit
pattern is decoded. For example, the pattern generation control circuit
generates and supplies an X address signal for selecting a word line to
the X address latch, and generates and supplies a Y address for selecting
a bit line to the Y address counter.
By combinations of test signals of four bits (one packet), 16 control
signals can be generated at the maximum. By combining a part (n) of the
control signal and the next packet, (n.times.16) control signals can be
generated. Further, by combining unused parts (m) in the above two
packets, (m.times.16) control signals can be generated. It is sufficient
to generate all of control signals necessary for operations of testing a
memory circuit.
To determine whether input signals supplied from the data input/output
terminals DQ0 to DQ3 are the test signal or not, the pad CKEP is used.
Specifically, by combining this signal CKEP, the clock signal CLK, and the
chip select signal CS/, the data input signal in normal operation and a
test signal in test operation are discriminated from each other.
With such a configuration, the number of pads necessary for electrical
contact at the time of a testing operation is largely reduced to 15 per
memory chip. By decreasing the number of contact pads in such a manner,
the number of memory chips contacted simultaneously with a conventional
probe card can be largely increased. The test time can be substantially
largely shortened.
While increasing the number of chips to be measured simultaneously, and
while assuring all of testing operations necessary for an operation test
on a memory circuit by serially inputting one or a plurality of test
signals as a packet, in order to make setting of an operation test at high
speed, the following is devised.
The four data input/output terminals DQ0 to DQ3 are also used for
outputting a test result. Although not particularly limited, the SDRAM has
four memory banks, and a test is conducted by simultaneously operating the
four memory banks. The test result generated every memory bank is
outputted through the data input/output terminals DQ0 to DQ3. Therefore,
test read data of every four memory banks is outputted and compared with
an expectation value by an external tester.
Using four bits of signals to conduct a test is very convenient for the
SDRAM. From the viewpoint of a testing operation, two bits are
insufficient as information for setting a testing operation, as will be
described hereinlater. A bit pattern of eight bits is too large, so that a
waste occurs, and the number of test terminals increases.
FIG. 2 is a timing chart of an example of an input protocol of test signals
in a semiconductor memory device according to the invention.
In the embodiment, although not particularly limited, three formats A to C
are prepared. The first format A is constructed by one cycle (one packet)
in which an operation command of a high use frequency is set. The second
format B is constructed by two cycles (two packets) in which an operation
command of a low use frequency is set. The third format is constructed by
four cycles (four packets) and is used to set various registers in a
memory by combining two second formats.
In the first format A, an input mode of a test signal is designated by the
high level of the clock CKEP, the high level of the clock signal CLK, and
the low level of the chip select signal CS/. A packet decoder
corresponding to the first format A receives a four-bit test signal (first
primary signal) RP1 entered as a command itself from the data input/output
terminals DQ0 to DQ3, decodes it, and starts operation ST/OP immediately
in the second cycle.
In the second format B, similarly, by the high level of the signal CKEP,
the high level of the clock signal CLK, and the low level of the chip
select signal CS/, an input mode of the test signal is designated. The
chip select signal CS/ is set to the low level for two cycles. A packet
decoder corresponding to the second format B discriminates that a four-bit
signal entered from the data input/output terminals DQ0 to DQ3 as the test
signal (first primary signal) RP1 is "OTHR" (refer to the following),
receives a four-bit test signal (second primary signal) RP2 entered in the
second cycle as a command, decodes the test signal RP2, and starts
operation ST/OP in the third cycle.
In the third format C, similarly, by the high level of the signal CKEP, the
high level of the clock signal CLK, and the low level of the chip select
signal CS/, the input mode of the test signal is designated. The chip
select signal CS/ is set to the low level twice each time for two cycles.
A packet decoder corresponding to the third format C discriminates that
the four-bit test signal (first primary signal) RP1 entered from the data
input/output terminals DQ0 to DQ3 is set to "OTHR" (refer to the
following), receives the four-bit test signal (second primary signal) RP2
entered in the second cycle as information of a designated register,
discriminates that a four-bit test signal (first secondary signal) RS1
entered in the third cycle is set to "REG" (register mode), receives a
four-bit test signal (second secondary signal) RS2 entered in the fourth
cycle as a command, and performs an operation on the register designated
in the second cycle.
In the case of using the test signals (packets) as the primary (first)
signals in two cycles and the secondary (latter) signals in two cycles,
the configuration of the packet decoders can be made simpler as will be
described hereinlater. In other words, by constructing the decoder in two
stages in correspondence with the two cycles, the formats B and C can be
constructed by similar circuits. The format A can be discriminated from
the format B by the combination with the chip select signal CS/. In the
format A, a command can be executed from the second cycle.
FIG. 3 is a diagram for explaining bit patterns corresponding to the format
A in FIG. 2 and their operations.
To the format A, five commands of NOP (no operation), PRE (precharge), READ
(read), WRIT (write), and ACTV (bank active) of a high use frequency in
operation commands of an SDRAM are assigned. The READ and WRIT commands
are accompanied with a column (Y) address control, and the ACTV command is
accompanied with a row (X) address control.
For each of the three commands READ, WRIT, and ACTV, four kinds of address
controls are performed. Specifically, in each of the commands READ and
WRIT, "0" denotes that the Y address is set to 0, "hold" denotes that the
address Y of the current cycle is held, +BL denotes that a value BL set in
the register is added to the address Y of the current cycle (Y+BL), and
-BL indicates that the value BL set in the register is subtracted from the
address Y of the current cycle. In the ACTV command as well, in a manner
similar to the above, "0" denotes that the X address is set to "0", "hold"
denotes that the address X of the current cycle is held, +XL denotes that
a value XL set in the register is added to the address X of the current
cycle (Y+BL), and -XL denotes that a value XL set in the register is
subtracted from the address X of the current cycle (X-XL).
By the command as described above, 14 bit patterns are used by the test
signal (packet) of four bits. To the remaining two bit patterns, the
above-described command "OTHR" instructing reference to the next packet
and "REG" instructing a register mode are assigned.
In the format B, operation commands having not so high use frequency in the
operation commands of the SDRAM, for example, eight commands of PALL (all
bank precharge), CBR (automatic refresh), SELF (self refresh), BST (burst
stop), PWRDN (power down mode), SELFX (self refresh end), and mode setting
such as "auto precharge enable" and "auto precharge mode disable" are
assigned. Although the bit patterns of the test signal RP2 with respect to
the commands will not be described, 16 commands can be designated at the
maximum by the combination with the test signal RP1=OTHR. Consequently,
after assigning the above eight commands, eight commands are still
available and can be used for setting the kind of a register of the format
C.
In the format C, although each of the bit patterns will not be described,
in the test signal RP2, any of the operation commands of the SDRAM is used
as register setting. For example, setting of a mode register, selection of
a bank, setting of a vendor test, or trimming select of VPP, VDLA, or VDLP
is assigned. In the secondary test signal RS1, by combination with the
test signal RS1 (=RP1) =REG, 16 register operations at the maximum with
respect to each of the registers designated by the test signal RP2 can be
set.
FIG. 4 is a diagram of the structure of pads of an SDRAM according to the
invention as an example. In an SDRAM, pads corresponding to terminals to
be connected with external terminals and pads used for a probing test are
formed. Pads to be connected to external terminals are mounted on a
package of 54 pins including three pairs of power source terminals *VCC
and *VSS on both ends and the center of the package and two pairs of *VCCQ
and *VSSQ for output circuit. As pads used for the test circuit according
to the invention, as shown in FIG. 1, 15 pads are used which are the clock
CLK, chip select CS/, data input/output DQ0 to DQ4, power sources VCC and
VSS to be connected to the external terminals and, in addition, the
substrate potential VBB, word line step-up voltage VPP, peripheral circuit
potential VDLP, array potential VDLA, bit line precharge potential VBLR,
plate potential VPLT, and mode entry pad CKEP.
That is, out of about 60 pads formed on an SDRAM, electrical contact is
made on the 15 pads to conduct an operation test on a memory circuit.
Conversely, electrical contact is not made on the control terminals CKE,
RAS/, CAS/, and WE/ and, in addition, the address terminals A0 to A13, the
data input/output terminals DQ4 to DQ15, power source terminals VCCQ and
VSSQ for output circuit, and mask terminals DQMU and DQML for input/output
circuit with a blank in the option-3. By the test signal (packet) entered
from the data input/output terminals DQ0 to DQ3, internal signals such as
an operation command and an address signal of an SDRAM are generated.
FIG. 5 is a block diagram showing an example of a test circuit to be
mounted on the SDRAM according to the invention.
The test circuit includes a plurality of packet decoders provided in
correspondence with circuits to be tested. Particularly, when a circuit to
be tested is a row address latch XAD-L, as well as a packet decoder PDEC2,
an arithmetic circuit ALU2 for generating a row address signal is added.
To a column address counter YCNT, as well as a packet decoder PDEC1, an
arithmetic circuit ALU1 for generating a column address signal is added.
For the computing circuit ALU2, a sub register s-xreg is provided. By using
a configuration such that one of registers xreg and s-xreg is switched and
connected to the computing circuit ALU2 and by allowing the sub resister
s-xreg to generate a refresh address, switching between a test address and
a refresh address can be easily made. It is also possible to use both of
the two resisters for a testing operation and perform non-continuous
address switching.
For a timing generator, a packet decoder PDEC3 is provided. For mode
registers MRG1 and MRG2, packet decoders PDEC4 and PDEC5 are provided,
respectively. For a timing generator TREG, a packet decoder PDEC6 is
provided. In such a manner, a packet decoder is provided for each of the
circuits necessary for a control for the testing operation, and the packet
decoders PDEC1 to PDEC6 are connected to a data bus DBUS and a clock bus
CBUS, in parallel.
Test signals entered from the data input/output terminals DQ0 to DQ3 are
received via a data input buffer DIB and transferred to the data bus DBUS.
Each of the packet decoders PDEC1 to PDEC6 therefore receives the entered
test signal and, while discriminating whether the test signal is the
command assigned to itself or not, executes the command.
A packet control PC receives signals from the mode entry pad CKEP, clock
terminal CLK, and chip enable terminal CS/ and transmits a clock signal to
the clock bus CBUS. Two out of four lines of the clock bus CBUS are used
for clock signals JJB and KKB each obtained by frequency dividing the
clock signal to the half. Synchronously with the clock signal JJP, the
signals RP1 and RS1 are entered. Synchronously with the clock signal KKB,
the signals RP2 and RS2 are entered.
The circuits for a test operation are spread to the circuit blocks
necessary to be controlled as in the embodiment and simple circuits such
as the packet decoders are provided adjacent to the circuits, thereby
enabling gaps and empty spaces between circuit blocks to be utilized from
the viewpoint of layout. Consequently, a substantial increase in chip area
can be prevented.
FIG. 6 is a circuit diagram showing an example of the packet control PC and
the data input buffer DIB in FIG. 5.
The data input buffer DIB has a data latch circuit for latching signals
entered from the data input/output terminals DQ0 to DQ3. By the conditions
of the low level of the chip select signal CSB (CS/) and the high level of
the mode entry pad CKEP, a transfer MOSEET provided at an output section
of the data latch circuit is turned on, and the entered signal is sent as
a test signal to the data bus DBUS. The data latch circuit is constructed
by a transfer gate MOSFET for transmitting an input signal to a serially
connected CMOS inverter circuit and a transfer gate MOSFET for feedback
which latches the CMOS inverter circuit.
The packet control PC takes the form of a binary counter circuit by using
two through latch circuits similar to the above, and is made operative by
the CKEP and CSB to perform an operation of frequency-dividing an input
clock signal CLK, thereby generating two-phase clock signals JJB and KKB
of which cycle is twice as many as that of the clock signal CLK and which
are alternately outputted.
FIG. 7 is a circuit diagram showing an example of the packet decoder PDEC
in FIG. 5. In the diagram, decoders corresponding to the signals RP1 (RS1)
and RP2 (RS2) are shown.
In the decoder corresponding to the format A, the signals READ, WRIT, and
ACTV are generated by gate circuits for receiving signals PK2B and PK3B of
the upper two bits from packet signals PK0B to PK3B of four bits supplied
via the data input buffer DIB. The signals PK0B and PK1B of the lower two
bits are decoded by gate circuits (not shown) and four commands (0, hold,
+ and -) are added to the signals READ, WRIT, and ACTV. An address control
as described above using the arithmetic circuit ALU is also added. The
commands of the precharge PRE, no operation NOP, other OTHR, and register
mode REG are generated by the gate circuits for receiving the four-bit
signals PK0B to PK3B. The clock signal JJB is supplied to the gate
circuits for generating the commands, and input signals entered in the
first and third cycles are decoded.
The signal OTHR is latched by the latch circuit on the basis of the clock
signal JJB, and the operations of the gate circuits corresponding to the
packet signals PK0B to PK3B are made effective by the signal OTHR and the
clock signal KKB subsequently entered. By the gate circuits, signals of
the commands PALL, CBR, SELF, BST, PWRDN, SELFX, APEN (auto precharge
enable), and APDE (auto precharge disable) corresponding to the format B
are generated. The signals APEN and APDE are supplied to a latch circuit
constructed by a gate circuit where the auto precharge signal AP is
generated.
Although not shown, in correspondence with the format C, a register is
designated by combination of the remaining signals RP2, the command REG is
generated by the signal RS1 supplied synchronously with the clock signal
JJB of the next cycle, and a signal for operating the register is
generated by a gate circuit for decoding the packet signals PK0B to PK3B
supplied synchronously with KKB.
A plurality of gate circuits as described above are not constructed as one
packet decoder. For example, the gate circuit for generating the commands
READ and WRIT is included in the packet decoder PDEC1 provided adjacent to
the column address counter shown in FIG. 5, and the gate circuit for
generating the command ACTV is provided adjacent to the row address latch
XAD-L shown in FIG. 5. The circuits for generating the commands are
provided so as to be spread in the circuit blocks corresponding to the
respective functions. As described above, the packet decoder is
constructed by a simple gate circuit. By disposing the packet decoders so
as to be spread to circuits to be controlled, gaps and empty spaces
between circuit blocks can be utilized from the viewpoint of a layout.
Consequently, a substantial increase in chip area can be prevented.
FIG. 8 is a circuit diagram showing an example of the arithmetic circuit
ALU in FIG. 5. In the example, a circuit of four bits is illustrated as a
representative. The arithmetic circuit ALU in the example is to generate a
row (X) address signal and a column (Y) address signal for a testing
operation as described above. By limiting the function of the computing
circuit ALU to generation of an address, therefore, attempt is made to
simplify the circuit.
Specifically, an address signal for the testing operation is sufficiently
generated by not only simple increase or decrease in an address such as +1
or -1 but also setting of addresses of a discrete number such as +2 or -2.
In the example, the function of adding or subtracting a discrete number
such as +4 or -4 is also added. By combining the functions, an address can
be designated in a wide range. By adding "clear (0)" and "hold" for
holding the preceding state, designation of all of addresses for a testing
operation can be achieved.
By limiting the numbers of addition and subtraction to, for example, 1, 2,
and 4 as described above, in an actual arithmetic circuit, an arithmetic
circuit for each of the lower three bits can be realized by a simple
circuit similar to a half adder for inverting a value and generating a
carry when both of a value before addition and a value to be added are "1"
or inverting the value before addition when it is 0 in an adding
operation.
Specifically, two through latch circuits are connected in series, a gate
circuit is used as the through latch circuit on the input side and is
controlled by a control signal ZERO so that all of outputs of the latch
circuit at the front stage are forcedly set to 0. The output signals Q0 to
Q3 of the latch circuit on the output side and the like are fed back to
the input side and used to control two pairs of transfer gate circuits.
The first pair of transfer gate circuits is used to generate an addition
output of the bit. With respect to the least significant bit, when both an
addition signal AD1 and the output Q0 are "1", "0" is generated, and a
carry is generated through the second pair of transfer gate circuits. When
either the addition signal AD1 or the output Q0 is "1", the original
values are used.
An adding operation is performed by operating the two latch circuits by a
control signal PLUS to thereby generate the addition signal. A subtracting
operation is realized by controlling the second pair of transfer gate
circuits by a control signal MINUS to generate complement numbers such as
the outputs Q0 to Q3, and adding addition signals AB2 and AB4. When a
control signal HOLD becomes effective, control signals LS/ and LS of the
latch circuit on the rear side are generated, and unchanged signals of the
latch circuit on the front side are received as they are.
In the example, as a precondition, a simplified circuit as described above
is used as the arithmetic circuit, and only one of the addition signals
AB1, AB2, and AB4 becomes "1". The result of computation when an addition
signal of 2 or larger is set to 1 by mistake is not therefore guaranteed.
Although it is imperfect as a computing circuit, when the use is limited
to generation of an address signal for a testing operation, the drawbacks
are not so considered since the test circuit is used by a semiconductor
manufacturer who knows the function very well. It is unnecessary to
consider the case where the circuit is erroneously used.
FIG. 9 is a waveform chart for explaining an example of the operation of
the arithmetic circuit.
When the control signal ZERO goes high, an output of the NOR gate circuit
in the latch circuit on the front side in the computing circuit becomes 0,
the clock signals LS and LS/ are generated and latched by the latch
circuit on the output side, and all of the address signals become 0.
When the addition signal AB1 is set to the high level (1), an output node
X0 of the first pair of transfer gate circuits becomes 1. When the control
signal PLUS goes high, the clock signals LS and LT are generated, and an
output node Y0 of the latch circuit on the front side becomes 1 in
correspondence with 1 of the output node X0. When the control signal PULS
goes low, the clock signal LS also changes, and an output signal Z0 (Q0)
of the latch circuit at the rear side changes to 1. By the change in the
output signal Z0, the two transfer gate circuits are switched, the output
node X0 is changed to the low level "0" and the next bit X1 is changed to
"1". Subsequently, when the control signal PLUS is set to the high level,
the clock signals LS and LT are generated in a manner similar to the
above, and the output node Y0 of the latch circuit on the front side is
changed to "0", and the output node Y1 is changed to "1". When the control
signal PULS goes low, the clock signal LS also changes, and the output
signal Z0 (Q0) of the latch circuit on the back side is changed to 0, and
the output signal Z1 (Q1) is changed to 1. In such a manner, the address
signal increases by +1 each time. The addition signal AB1 is returned to
the low level for the next operation.
When the control signal HOLD goes high, only the clock signal LS is
generated, signals from the output nodes Y0 to Y3 and the like of the
latch circuit on the front side are supplied to the latch circuit on the
back side. Since the previous state is received as it is, no change occurs
in outputs Z0 to Z3 (Q0 to Q3) and the like.
When the addition signal AB2 is set to the high level, in the second bit,
the output node X1 is changed to the low level "0", and the next bit X2 is
changed to "1". Subsequently, when the control signal PLUS is set to the
high level, in a manner similar to the above, the output node Y1 in the
latch circuit at the front side changes to 0, and the output node Y2
changes to 1. When the control signal PULS goes low, the clock signal LS
also change, the output signal Z1 (Q1) of the latch circuit on the back
side changes to 0, the output signal Z2 (Q2) changes to 1, and addition of
+2 is executed.
When the addition signal AB2 goes low and the addition signal AB1 goes
high, the output node X0 changes to the high level. When the control
signal MINUS is set to the high level, the outputs Z0 to Z2 (Q0 to Q2) of
the lower three bits are inverted, complement numbers are generated, and
+1 of the AB1 is added. Consequently, the result of subtraction of -1 is
derived. When the addition signal AB1 goes low, the addition signal AB2
goes high, and the control signal MINUS goes high, the outputs Z0 to Z2
(Q0 to Q2) of the lower three bits are inverted, a complement number is
generated, +2 of the addition signal AB2 is added, and the result of
subtraction of -2 is generated. Similarly, when the control signal HOLD is
set to the high level, the result of calculation is maintained. When the
control signal ZERO is generated, all of the outputs Z0 to Z3 and the like
are cleared to 0.
For example, when an address step is set to +3, it can be realized by
performing two cycles of +1 and +2, or two cycles of +4 and -1. The
address step operation except for .+-.1, .+-.2, and .+-.4 can be
arbitrarily set by the combination. An address can be generated in the
testing operation by a relatively simple pattern. It can sufficiently
correspond to the limited computing function as described above.
FIG. 10 is a schematic layout sketch showing an example of the SDRAM
according to the invention. Each circuit block in the diagram is formed on
a single semiconductor substrate made of single crystal silicon or the
like by a known technique of fabricating a semiconductor integrated
circuit. The circuits in the diagram are drawn almost in accordance with a
geometrical arrangement on the semiconductor substrate. In the embodiment,
a memory array is divided into four pieces and memory banks Bank0 to Bank3
are formed.
The memory banks 0 to 3 are disposed in correspondence with the memory
array divided into four pieces of two pieces each in the upper and lower
sides and two pieces each in the right and left sides. In the center
portion in the longitudinal direction of the chip, peripheral circuits
including an address input circuit, and a data input/output circuit, and a
line of bonding pads are provided. In the peripheral circuits, to
rationalize the layout of the circuits which take the form of random logic
circuits, the random logic circuits and bonding pads are disposed in
parallel to each other.
In the example, the peripheral circuits and the bonding pad line are
arranged in parallel to each other. In the configuration, the bonding pad
line is disposed in a position deviated from the center line in the
longitudinal direction of the semiconductor chip. As a result, in the
center portion in the longitudinal direction of the semiconductor | | |
