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Wiring substrate and an electroless copper plating solution for providing interlayer connections
   
Document Number
US Patent 6831009
Issued Date
December 14, 2004
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Abstract
A multilayer wiring substrate which is high in connection reliability is provided through process steps of forming more than one opening, such as a via-hole in a dielectric layer laminated on a substrate, and then applying uniform copper plating to a surface portion of the dielectric layer including the opening to thereby form a wiring layer. An electroless copper plating solution with at least one of mandelonitrile and triethyltetramine mixed therein is used to perform the intended electroless copper plating. An alternative process makes use of a electroless copper plating solution with chosen additive agents or "admixtures" containing at least one of mandelonitrile and triethyltetramine plus eriochrome black T along with at least one of 2,2'-bipyridyl, 1,10-phenanthroline, and 2,9-dimethyl-1,10-phenanthroline.
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Number of Claims:
4
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Owner
Hitachi, Ltd. (Tokyo,JP)
Published
December 14, 2004
Application Number
09/962,249
Filed
September 26, 2001
US Classification
438/672   438/637
Int'l Classification
C23C   18/40   (20060101)   C23C   18/31   (20060101)   H05K   3/42   (20060101)  
Examiner
Priority Data
Oct 03, 2000 [JP] 2000-303997
USPTO Field of Search
438/618   438/675   438/637   438/638   438/639   438/640   438/700  
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