A microprocessor is provided whose power consumption is reduced optimally according to an execution instruction code and an operational mode. In addition to a first PLA used in a normal operation, a second PLA dedicated for execution of certain instructions frequently used in a slow mode is provided. When instruction codes and state signals to be executed in the slow mode match data set in the second PLA, the operation of the first PLA is stopped, and the microprocessor is controlled according to a microcode output from the second PLA.
