A hybrid memory system having electromechanical memory cells is disclosed. A memory cell core circuit has an array of electromechanical memory cells, in which each cell is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon. An access circuit provides array addresses to the memory cell core circuit to select at least one corresponding cell. The access circuit is constructed of semiconductor circuit elements.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation application of, and claims priority under 35 USC .sctn.120 to, U.S. patent application Ser. No. 09/915,095, filed Jul. 25, 2001 now U.S. Pat. No. 6,574,130, assigned to the assignee of this application.
This application is related to the following applications, all of which are filed on the same date that this application is filed, all of which are assigned to the assignee of this application, and all of which are incorporated by reference in their entirety:
Electromechanical Memory Array Using Nanotube Ribbons and Method for Making Same (U.S. patent application Ser. No. 09/915,093, filed Jul. 25, 2001); and,
Electromechanical Memory Having Cell Selection Circuitry Constructed with Nanotube Technology (U.S. patent application Ser. No. 09/915,173 filed Jul. 25, 2001).
USPTO Field of Search
365/129
365/151
Related Patents
7209019 - Switch - Owned by Matsushita Electric Industrial Co., Ltd. (Osaka,JP)
A switch comprises voltage applying means for providing direct current potentials to first to third beams arranged with a spacing slightly distant one from another, and electrodes for inputting/outputting signals to/from the beams. By controlling the direct current potential provided to the beam, an electrostatic force is caused to thereby change the beam positions and change a capacitance between the beams. By causing an electrostatic force between the first and second beams and moving the both beams, the first and second beams can be electrically coupled together at high speed. Also, an electrostatic force is caused on the third beam arranged facing to the first and second beams, to previously place it close to the first and second beams. When the electrostatic force is released from between the first and second beams, the second beam moves toward the third beam thereby releasing the first and second beams of an electric coupling.
Structures and methods for operating the same. The structure includes (a) a substrate; (b) a first and second electrode regions on the substrate; and (c) a third electrode region disposed between the first and second electrode regions. In response to a first write voltage potential applied between the first and third electrode regions, the third electrode region changes its own shape, such that in response to a pre-specified read voltage potential subsequently applied between the first and third electrode regions, a sensing current flows between the first and third electrode regions. In addition, in response to a second write voltage potential being applied between the second and third electrode regions, the third electrode region changes its own shape such that in response to the pre-specified read voltage potential applied between the first and third electrode regions, said sensing current does not flow between the first and third electrode regions.
A non-volatile memory device, and method of forming the same, increases or maximizes the performance of an ultramicro-structured device. In one embodiment, a non-volatile memory device comprises a first word line and a second word line insulated from each other and positioned to intersect each other with a vacant space therebetween; a bit line in the vacant space between one of the first word line and the second word line and positioned in parallel with one of the first word line and the second word line, the bit line constructed and arranged to be deflected toward one of the first word line and the second word line by an electric field induced between the first word line and the second word line; and a trap site between the bit line and one of the first word line and the second word line intersecting the bit line, the trap site being insulated from the one of the first word line and the second word line intersecting the bit line and spaced apart from the bit line by a portion of the vacant space, the trap site configured to trap a predetermined electric charge to electrostatically fix the bit line in a deflected position in the direction of the one of the word lines.
Structures for memory devices. The structure includes (a) a substrate; (b) a first and second electrode regions on the substrate; and (c) a third electrode region disposed between the first and second electrode regions. In response to a first write voltage potential applied between the first and third electrode regions, the third electrode region changes its own shape, such that in response to a pre-specified read voltage potential subsequently applied between the first and third electrode regions, a sensing current flows between the first and third electrode regions. In addition, in response to a second write voltage potential being applied between the second and third electrode regions, the third electrode region changes its own shape such that in response to the pre-specified read voltage potential applied between the first and third electrode regions, said sensing current does not flow between the first and third electrode regions.
