A shift-register circuit. The input circuit receives the input pulse and outputs a high-voltage level input signal when the input pulse is at high voltage level. The level shifting circuit includes a first PMOS transistor having a first gate, a first drain and a first source coupled to a first voltage VDD, a second PMOS transistor having a second gate coupled to the first drain, a second drain coupled to the first gate and a second source coupled to the first voltage VDD, a first inverse logic gate coupled to the first drain and having an output terminal, a second inverse logic gate coupled to the second drain and having an inverse output terminal coupled to the input circuit, a first NMOS transistor having a third gate coupled to the input circuit, a third drain coupled to the first drain and a third source coupled to a second voltage VSS, a second NMOS transistor having a fourth gate coupled to the second gate and a fourth drain coupled to the second drain and a fourth source coupled to the second voltage VSS. The output circuit is coupled to the output terminal for outputting the shift-register signal.
CROSS REFERENCE TO RELATED APPLICATIONS
Pursuant to 35 USC .sctn.119, this application claims the benefit of Taiwan Patent Application No. 91116797 filed Jul. 26, 2002.
